SC453TSTRT datasheet(12/23 Pages) SEMTECH

12 / 23 page

www.semtech.com

POWER MANAGEMENT

SC453

DAC Slew Control

The output of the DAC will slew at a rate deﬁned by the

current in the SS pin and the capacitor applied externally

to the SS pin. The slew rate (charge current) applied de-

pends on which mode (soft-start, VID or sleep transition)

is in effect. The SS capacitor together with the DAC ca-

pacitor will determine the stability of the DAC, a 1nF ca-

pacitor is recommended for the DAC pin.

Blanking During VID Changes

On any VID change or Sleep change, the PG# and PG_

DEL signals are blanked for 62 switching cycles to prevent

glitching during the transition.

Sleep Function

In sleep mode, the DAC output is set by the voltage on

the SLPV pin when the SLP pin is held high. In "VID Sleep"

mode, the DAC output is set by the VID bits when SLP is

held high. During sleep, the hysteresis and current limit

hysteresis currents are reduced to 70% of their nominal

values.

SLPV/VID Sleep Mode

By default, the controller is in "SLPV controlled Sleep"

mode. In this mode, the voltage applied to the SLPV pin

appears at the DAC output when SLP is asserted.

By holding the SLPV pin at VCCA during start-up, "VID con-

trolled sleep" mode is engaged. In this mode, the DAC out-

put continues to be set by the VID inputs even when SLP

is asserted.

CORE CONVERTER CONTROLLER

Core Comparator

This is an ultra-fast hysteretic comparator with a typical

propagation delay of about 20ns at a 20mV overdrive.

Hysteresis is generated by the current set at the HYS pin

impressed upon an external resistor connected to the

CMP pin.

Current Limit Comparator

The Current Limit Comparator monitors the core converter

output current and turns off the high side FETs when the

current exceeds the upper current limit threshold, VHCL

and is re-enabled only if the phase current drops below

the lower current limit threshold, VLCL. The current is

sensed by monitoring the voltage drop across the current

sense resistor, RCS connected in series with the core con-

verter inductor. VHCL and VLCL are ﬁxed by the current

set at the HYS pin impressed upon an external resistor

connected to the CLRF pin.

Current Limit Latch

If the CORE voltage goes lower than 14% below the VID

(i.e., out of the power good window), then sustained cur-

rent limiting (32 current limit pulses) will cause the part

to permanently latch off. The latch is inhibited during soft-

start.

Core Converter Soft-Start Timer

This block controls the start-up ramp time of the CORE

voltage up to the boot voltage. The primary purpose is to

reduce the initial in-rush current on the core input voltage

(battery) rail.

Cycle-by-Cycle Power-Save

A zero crossing comparator detects when the currents

through the external sense resistor reduces to zero. When

the current in the external sense resistor reaches zero,

the bottom FET is latched off. The latch is reset when the

controller decides to switch on the top FET. This prevents

excessive switching at light loads and hence saves switch-

ing power losses.

Applications Information (Cont.)

SC453TSTRT датащи(PDF) 12 Page - Semtech Corporation

SC453TSTRT датащи(HTML) 12 Page - Semtech Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

датащи скачать

ссылки URL