SC2545TSTRT datasheet(9/24 Pages) SEMTECH

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SC2545

POWER MANAGEMENT

The inductor current is sensed by using the low side

MOSFET R

ds(on) . After low side MOSFET is turned on,

the OCP comparator starts monitoring the voltage

drop across the MOSFET. The OCP trip level is pro-

grammed by the resistor from the ILIM pin to the

phase node. There is an internal current source that

flows out of the ILIM pin which will generate a voltage

drop on the setting resistor. When the sum of the

setting resistor voltage and the MOSFET drain to

source voltage is less then zero, the OCP condition will

be flagged. This functionality is depicted in Figure 2.

The following formula is used to set the OCP level

Figure 2. Block diagram of over current

protection.

Figure 3. OCP comparator timing chart.

Over Current Protection (OCP)

()

ILIM

L PEAK

DS ON

µ ×=

When OCP is tripped, both high side and low side

MOSFETs will be turned off and this condition is

latched. At the same time, the soft start cap will be

discharged by the internal current source of 15uA.

When the Vss drops bellow 0.65V, the DRVL pin will go

high again.

To avoid switching noise during the phase node

commutation, a 100nS blanking time is built in after

the low side MOSFET is turned on, as shown in Fig. 3.

10uA

OCP

DRVL

ILIM

Out

OUTPUT

VCC

DRVH

Under V

nder V

nder Voltage Lock Out (UVL

oltage Lock Out (UVL

oltage Lock Out (UVLO)

The UVLO circuitry monitors Vcc and the soft start

begins once Vcc ramps up above 4.5V. There is a built

in 200mV hysteresis for the UVLO ramp down

threshold. The gate driver output will be in “tri-state”

(both high side and low side MOSFET off) once Vcc

ramps down bellow 4.2V (typical), and the soft start

cap will be discharged by internal 15uA current sink.

Over V

er V

er Voltage Pr

oltage Pr

oltage Proooootttttection (O

ection (O

ection (OVP)

VP)

The OVP circuitry monitors the feedback voltages, If

either feedback voltage exceeds 0.89V, the OVP

condition is registered. Under this condition, the DRVH

pins will be pulled low, and the DRVL pins will be pulled

high. This will create a “crow bar” condition for the

input power rail in case the high side MOSFET is failed

short. The crow bar operation may trip the input supply

to prevent the load from seeing more voltage.

Power Good Output

The power good is an open collector output. The

PWRGD pin is pulled low at start up if any of the two

feedback voltages below 90% of its regulation level.

The ramp down threshold of the signal is 80% of the

regulation target. External pull up is required for the

PWRGD pin, and the pull up resistor should be chosen

such that the pin does not sink more than 2mA when

PWRGD is low.

100nS

Blanking

OCP Active

100nS

Blanking

OCP Active

Applications Information (Cont.)

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