HT82K28A datasheet(6/16 Pages) HOLTEK

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HT82K28A

Rev. 1.30

June 27, 2002

¨ Bit 7=0 (always)

Delay= (1+bit6,bit5)

´ 250ms

Typematic rate= 1/period

...where period= (8+A)

´ (2^B) ´ 0.00417

...where A= binary value of bit 2, 1 and 0

...where B= binary value of bit 4 and 3

b4~b0

Typematic

rate

b4~b0

Typematic

rate

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

30.0

26.7

24.0

21.8

20.0

18.5

17.1

16.0

15.0

13.3

12.0

10.9

10.0

9.2

8.6

8.0

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

7.5

6.7

6.0

5.5

5.0

4.6

4.3

4.0

3.7

3.3

3.0

2.7

2.5

2.3

2.1

2.0

· Default

¨ delay: 500ms

± 20%

¨ typematic rate=10.9 characters/sec

± 20%

Commands to the system

00: keyboard detect a error/overrun (set 2, set 3)

AB,83: keyboard ID

AA: BAT completion

FC: BAT failure

EE: Echo

FA: Acknowledge

FE: Resend

FF: Keyboard detects a overrun (set 1)

· FA: Acknowledge

If the KB (Keyboard) receives any valid input except

EE (echo) and resend (FE) then send an FA to the

system first.

If the command is EE, then send an EE back to the

system.

If the command is FE, then send the last key code to

system.

If there is an interrupt while sending FA, the KB dis-

cards the FA and accepts the command from the sys-

tem and processes it.

· 00/FF: Key overrun

If the keyboard detects an overrun error, the KB sends

an overrun error code to the system.

mode 1: FF

mode 2,3: 00

· FE: Resend

The KB issues an FE when there is a parity error in

transmission.

Data communications

· Data output

¨ If CLK=0, no transmission (keyboard inhibited).

¨ If CLK=1, DATA=0, no transmission (system re-

quest to send).

¨ If CLK=1, DATA=1, transmission permitted.

¨ Data will be valid before the trailing edge and be-

yond the leading edge of the clock.

¨ The KB checks the clock line for an active level at

least every 60ms.

¨ If line contention occurs (system brings the clock

low before the tenth clock), set clock=data=high.

· Data input

¨ The system overrides the clock line for at least

60ms

¨ The keyboard checks the state of the clock line at

intervals of no more than 10ms

¨ If a system request-to-send is detected, the key-

board counts 11 data bits.

¨ Data will be valid before the rising edge and beyond

the falling edge

¨ After the 10th bit, the keyboard checks for an active

level on the

²data² line. If the line is active it is forced

to be inactive, and counts one more bit.

Note:

This action signals the system that the

keyboard has received its data. Upon

reception of this signal, the system returns

to the ready state, in which it can accept

keyboard outputs or goes to the inhibit state

until it is ready.

If the keyboard

²data² line is found to be at an inactive

level following the 10th bit, a frame error has occurred,

and the keyboard continues to count until the

²data²

line becomes active. The keyboard then makes the

²data² line inactive and sends a Resend.

Data stream

Mode 1,2,3

B1:

B2:

b3:

b4:

b5:

b7:

b8:

b9:

b10:

b11:

start bit

always 0

data bit 0

data bit 1

data bit 2

data bit 3

data bit 4

data bit 5

data bit 6

data bit 7

parity bit

(odd par)

stop bit

always 1

Note:

The parity bit is either 1 or 0, and the 8 data bits,

plus the parity bit, always have an odd number

of 1

¢s.

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