SC900 datasheet(10/23 Pages) SEMTECH

10 / 23 page

 2005 Semtech Corp.

www.semtech.com

POWER MANAGEMENT

SC900

Applications Information

General Description

Each of the five low-dropout linear regulators (LDOs) can

be independently enabled or disabled and their output

voltages can each be set by an independent DAC. These

controls can be accessed through the I2C serial port.

There are five 8-bit volatile registers in the SC900; one

for each LDO (registers A,B,C,D,E). In addition there is

one common reset and power good control register and

one on/off control register. The active shutdown circuitry

can be accessed through each LDO register (refer to the

section “Active Shutdown” on page 11 for more informa-

tion).

At power-up, the register contents are reset to their de-

fault values and the ARST for LDO A has a default start-

up delay of 100ms. At any time the part can be put into

it’s lowest power state (shutdown) by pulling the EN pin

low. Whenever the EN pin is forced low, the previous

settings are lost and the part requires reprogramming to

return to the desired state. When EN is pulled high, the

device starts up in the default state. A detailed descrip-

tion of the protocol used to load the registers with data

is described in the section entitled “Using the I2C Inter-

face” on page 13.

VIN and Enable Pin

The VIN supply must be

≥ 2.7V before the EN pin can be

asserted. This means that the EN pin should not be tied

to VIN so that it does not reach a logic high level before

the input supply reaches 2.7V.

LDOA (Core Supply)

LDOA is intended to be used as the MSM core supply. It

has an output current capability of 200mA and a dedi-

cated reset signal ARST. INA is the dedicated input sup-

ply for this regulator.

LDOB (Digital I/O Supply)

INB supplies power for the internal I2C interface and other

digital I/O functions, while LDOB supplies power for ARST

and LDOPGD output ports (see block diagram). There-

fore it is imperative that LDOB be operational to make

use of ARST and LDOPGD. If LDOB is turned off by the

on/off control register, these output ports will not func-

tion.

LDO RESET Control Register:

ARST Pin

There are two functions that can be programmed, defin-

ing the ARST pin action:

• Set the polarity of the reset signal

• Set the reset clear delay time in milliseconds

As soon as the LDOA output voltage falls below its pro-

grammed value, the ARST pin is asserted. The polarity

of the ARST pin can be set to active high or active low

during a reset condition, by bit 6 of the LDO Reset Con-

trol Register. Once the error condition is resolved (out-

put rises to the programmed value), a delay is initiated

before the ARST pin is cleared. The delay is program-

mable by bits 0-1 of the LDO Reset Control Register. The

Default delay time is 100ms, and the delay can be pro-

grammed for 0, 50, 100, or 150ms.

LDOPGD Pin

There are three functions that can be programmed to

define the LDOPGD pin action:

• Set which LDOs are to be monitored for power-good

• Set the polarity of the power-good signal

• Set the power-good delay time in milliseconds

Bits 4 and 5 of the LDO Reset Control Register select

which LDO or LDOs are monitored. LDO C, D and E can

be monitored independently or LDOs A, C, D, & E can be

monitored collectively. The polarity of the LDOPGD pin

can be set to active high or active low by bit 7 of the LDO

Reset Control Register. As soon as any of the selected

LDO output voltages which are monitored falls within spec,

the LDO power-good (LDOPGD) pin is asserted. Once the

LDO output power is stable (output rises to the pro-

grammed value), a delay is initiated before the LDOPGD

pin is set. The delay is programmable by bits 2 and 3 of

the LDO Reset Control Register. The default delay is

100ms, and this delay can be programmed to 0, 50,

100, or 150ms.

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