HT49CV3 datasheet(16/44 Pages) HOLTEK

16 / 44 page

HT49RV3/HT49CV3

Rev. 1.30

March 20, 2007

Reset

(Power-on)

WDT Time-out

(Normal Operation)

RES Reset

(Normal Operation)

RES Reset

(HALT)

WDT Time-out

(HALT)*

INTC0

-000 0000

-uuu uuuu

INTC1

-000 -000

-uuu -uuu

RMTC

0000 000-

uuuu uuu-

MFIS

---0 0000

---u uuuu

RTCC

---0 -111

---u -uuu

1111 1111

uuuu uuuu

PAC

1111 1111

uuuu uuuu

---- 1111

---- uuuu

PBC

---- 1111

---- uuuu

1--- ----

u--- ----

PCC

1--- ----

u--- ----

1111 ----

uuuu ----

PDC

1111 ----

uuuu ----

SBCR

0110 0000

uuuu uuuu

SBDR

xxxx xxxx

uuuu uuuu

RMT0

0000 0000

uuuu uuuu

RMT1

0000 0000

uuuu uuuu

VFDC

0000 -111

Note:

²*² stands for ²warm reset²

²u² stands for ²unchanged²

²x² stands for ²unknown²

Timer/Event Counter

Two timer/event counters (TMR0,TMR1) are imple-

mented in the microcontroller. The Timer/Event

Counter 0 contains a 16-bit programmable count-up

counter and the clock may come from an external

source or an internal clock source. An internal clock

source comes from fSYS. The Timer/Event Counter 1

contains a 16-bit programmable count-up counter

and the clock may come from an external source or

an internal clock source. An internal clock source co-

mes from fSYS/4 or 32768Hz selected by option. The

external clock input allows the user to count external

events, measure time intervals or pulse widths, or to

generate an accurate time base.

There are six registers related to the Timer/Event

Counter 0 and Timer/Event Counter 1; TMR0H

(0CH), TMR0L (0DH), TMR0C (0EH) and the

Timer/Event Counter 1, TMR1H (0FH), TMR1L (10H),

and TMR1C (11H). Writing TMR0L (TMR1L) will only

place the written data to an internal lower-order byte

buffer (8-bit) and writing TMR0H (TMR1H) will trans-

fer the specified data and the contents of the

lower-order byte buffer to TMR0H (TMR1H) and

TMR0L (TMR1L) registers, respectively. The

Timer/Event Counter 1/0 preload register is changed

by each writing TMR0H (TMR1H) operations. Read-

ing TMR0H (TMR1H) will latch the contents of TMR0H

(TMR1H) and TMR0L (TMR1L) counters to the destination

and the lower-order byte buffer, respectively. Reading the

TMR0L (TMR1L) will read the contents of the lower-order

byte buffer. The TMR0C (TMR1C) is the Timer/Event

Counter 0 (1) control register, which defines the operating

mode, counting enable or disable and an active edge.

The TM0 and TM1 bits define the operation mode. The

event count mode is used to count external events, which

means that the clock source is from an external (TMR0,

TMR1) pin. The timer mode functions as a normal timer

with the clock source coming from the internal selected

clock source. Finally, the pulse width measurement mode

can be used to count the high or low level duration of the

external signal (TMR0, TMR1), and the counting is based

on the internal selected clock source.

In the event count or timer mode, the timer/event counter

starts counting at the current contents in the timer/event

counter and ends at FFFFH. Once an overflow occurs, the

counter is reloaded from the timer/event counter preload

of the INTC0, T1F; bit 4 of the INTC1). In the pulse width

measurement mode with the values of the TON and TE

bits equal to 1, after the TMR0 (TMR1) has received a tran-

sient from low to high (or high to low if the TE bit is

²0²), it

will start counting until the TMR0 (TMR1) returns to the

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