HT48RA3 datasheet(15/38 Pages) HOLTEK

15 / 38 page

HT48RA3/HT48CA3

Rev. 1.30

October 12, 2007

T 0 M 1

T 0 M 0

T M R 0

T 0 E

T 0 M 1

T 0 M 0

T 0 O N

P u l s e W i d t h

M e a s u r e m e n t

M o d e C o n t r o l

T i m e r / E v e n t C o u n t e r 0

P r e l o a d R e g i s t e r

8 - b i t

T i m e r / E v e n t C o u n t e r

( T M R 0 )

D a t a B u s

R e l o a d

P F D

8 - s t a g e P r e s c a l e r

8 - 1 M U X

f S Y S

f I N T

T 0 P S C 2 ~ T 0 P S C 0

( 1 / 2 ~ 1 / 2 5 6 )

¸ 2

O v e r f l o w t o I n t e r r u p t

Timer/Event Counter 0

There are 3 registers related to Timer/Event Counter 1;

TMR1H (0FH), TMR1L (10H), TMR1C (11H). Writing

TMR1L will only put the written data to an internal

lower-order byte buffer (8 bits) and writing TMR1H will

transfer the specified data and the contents of the

lower-order byte buffer to TMR1H and TMR1L preload

registers, respectively. The Timer/Event Counter 1

preload register is changed by each writing TMR1H op-

erations. Reading TMR1H will latch the contents of

TMR1H and TMR1L counters to the destination and the

lower-order byte buffer, respectively. Reading the

TMR1L will read the contents of the lower-order byte

buffer. The TMR1C is the Timer/Event Counter 1 control

able or disable and active edge.

The T1M0, T1M1 bits define the operating mode. The

event count mode is used to count external events,

which means the clock source comes from an external

(TMR1) pin. The timer mode functions as a normal timer

with the clock source coming from the instruction clock.

The pulse width measurement mode can be used to

count the high or low level duration of the external signal

(TMR1). The counting is based on the instruction clock.

In the event count or timer mode, once the Timer/Event

Counter 1 starts counting, it will count from the current

contents in the Timer/Event Counter 1 to FFFFH. Once

overflow occurs, the counter is reloaded from the

Timer/Event Counter 1 preload register and generates

the corresponding interrupt request flag (T1F; bit 6 of

INTC) at the same time.

In pulse width measurement mode with the T1ON and

T1E bits are equal to one, once the TMR1 has received

a transition from low to high (or high to low if the T1E bit

is 0) it will start counting until the TMR1 returns to the

original level and reset the T1ON. The measured result

will remain in the Timer/Event Counter 1 even if the acti-

vated transition occurs again. In other words, only one

cycle measurement can be done. Until setting the

T1ON, the cycle measurement will function again as

long as it receives further transition pulse. Note that, in

this operating mode, the Timer/Event Counter 1 starts

counting not according to the logic level but according to

the transition edges. In the case of counter overflows,

the counter 1 is reloaded from the Timer/Event Counter

1 preload register and issues the interrupt request just

like the other two modes.

To enable the counting operation, the timer ON bit

(T1ON; bit 4 of TMR1C) should be set to 1. In the pulse

width measurement mode, the T1ON will be cleared au-

tomatically after the measurement cycle is complete.

But in the other two modes the T1ON can only be reset

by instructions. The overflow of the Timer/Event Coun-

ter 1 is one of the wake-up sources. No matter what the

operation mode is, writinga0to ET1I can disabled the

corresponding interrupt service.

In the case of Timer/Event Counter 1 OFF condition,

writing data to the Timer/Event Counter 1 preload regis-

ter will also load the data to Timer/Event Counter 1. But

if the Timer/Event Counter 1 is turned on, data written to

the Timer/Event Counter 1 will only be kept in the

T 1 M 1

T 1 M 0

T M R 1

T 1 E

T 1 M 1

T 1 M 0

T 1 O N

P u l s e W i d t h

M e a s u r e m e n t

M o d e C o n t r o l

1 6 - b i t

T i m e r / E v e n t C o u n t e r

P r e l o a d R e g i s t e r

D a t a B u s

R e l o a d

O v e r f l o w

t o I n t e r r u p t

1 6 - b i t

T i m e r / E v e n t C o u n t e r

( T M R 1 H / T M R 1 L )

L o w B y t e

B u f f e r

f S Y S / 4

Timer/Event Counter 1

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