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 2004 Semtech Corp.

www.semtech.com

POWER MANAGEMENT

SC4150

With the input bias current of the UV and OV comparators

in the range of 20-30nA, let’s choose the R1 to be

562k

10.2k

which is quite acceptable for those functions.

Resistor R4 sets the over-current trip. To choose R4,

the user must determine the level of the current where

it should trip. As a rule of thumb, the over-current is set

to be 200-300% of the nominal value. In our case, we

assumed this value to be 5A.

Considering the minimum trip voltage is 50mV the value

of R4 is 50mV ÷ 5A = 10 m

The tolerance of this resistor is usually price driven and

5% is an adequate range of accuracy.

The actual position and layout of the circuitry around the

sense resistor R4 is critical to avoid a false over-current

tripping. The trace routing between R4 and SC4150

should be as short as possible and wide enough to handle

the maximum current with zero current in the sense lines

– ideally “Kelvin” like.

Additionally, there is a short delay circuit at the

comparator to filter out unwanted noise and otherwise

induced transients.

Inrush Current is being controlled by the R5C3 network

and swamping capacitor C2.

When a board is plugged into a live backplane, the input

bulk capacitance of the board’s power supply produces

large current transients due to the rush of the currents

charging those capacitors. The main feature of the

SC4150 is to provide an orderly and well-controlled inrush

current.

Since the minimum trip voltage is 50mV, let’s choose

the inrush current to be 3A.

Imax = Cload ·

dt = Cload ·

This would be the minimum time for the gate voltage

plateau during which the Vdd linearly decreases

maintaining 3A charge current of the Cload.

The inrush can be calculated using the following equation:

I

With the values shown in the schematic the actual inruch

current will be about 2A, which is within the limits we

have chosen.

Resistor R5 will produce a time constant which prevents

Q1 from turning on when power is initially applied and

the circuit is not ready to actively pull the gate low. It’s

value is not critical and 18k ensures the adequate delay.

The value of C2 is chosen to prevent false turn-on of the

FET due to the current flowing via C3 into the gate of the

FET when the circuit initially connects to the power source.

Capacitors C2 and C3 form a divider from Vin to GND.

C2 must keep the initial voltage at the gate below Vth

minimum.

For the typical FET, this threshold is around 1V to 2V,

therefore C2 = 100 • C3 will keep gate voltage at 0.7V,

even at the ”worst” case of Vin = 70V.

The choice of the Q1 is quite straightforward and is guided

mostly by thermal considerations due to the power

dissipation in the steady state.

For instance, in our case, the nominal current is 2A, the

power dissipation due to the conducting losses will be

Pdis = Inom² • Rds_on.

The MOSFET should be able to withstand Vdss

with continuous drain current Id

Ω,

and will dissipate

Pdis = 2² • 0.2 = 0.8W, which can be handled by this

DPAK device.

If there is a consideration of reducing the temperature

of the MOSFET then the lower Rds_on device should be

chosen or a different style (D2PAK) which has lower

Junction-to-Ambient thermal characteristics.

The R6 has a function of dumping high frequency

oscillations. The value of it is not critical and can be in

the range of 5

Ω to 20Ω.

Applications Information (Cont.)