XIO2000A datasheet(29/155 Pages) TI

29 / 155 page

Introduction

April 2007

SCPS155B

Table 2−11. Miscellaneous Terminals (Continued)

SIGNAL

GZZ

ZZZ

BALL

ZHH

BALL

I/O

TYPE

CELL

TYPE

CLAMP

RAIL

EXTERNAL

PARTS

DESCRIPTION

GPIO6

U07

M05

I/O

CMOS

VDD_33

−

General-purpose I/O 6. This terminal functions as a

GPIO controlled by bit 6 (GPIO6_DIR) in the GPIO

control register (see Section 4.59).

Note: This terminal has an internal active pullup

resistor.

GPIO7

U08

L06

I/O

CMOS

VDD_33

−

General-purpose I/O 7. This terminal functions as a

GPIO controlled by bit 7 (GPIO7_DIR) in the GPIO

control register (see Section 4.59).

Note: This terminal has an internal active pullup

resistor.

GRST

N17

L13

CMOS

VDD_33_

COMBIO

−

Global reset input. Asynchronously resets all logic in

device, including sticky bits and power management

state machines.

Note: The GRST input buffer has both hysteresis and

an internal active pullup.

LOCK

U04

P02

I/O

PCI

Bus

VCCP

Pullup

resistor per

PCI spec

This terminal functions as PCI LOCK when bit 12

(LOCK_EN) is set in the general control register (see

Section 4.65).

Note: In lock mode, an external pullup resistor is

required to prevent the LOCK signal from floating.

M66EN

R01

M01

PCI

Bus

VCCP

Pullup

resistor per

PCI spec

66-MHz mode enable

0 = Secondary PCI bus and clock outputs operate at

33 MHz

1 = Secondary PCI bus and clock outputs operate at

66 MHz

Note: If the PCI bus clock is always 33 MHz, then this

terminal is connected to VSS.

SERIRQ

T04

N03

I/O

PCI

Bus

VCCP

Pullup or

pulldown

resistor

Serial IRQ interface. This terminal functions as a serial

IRQ interface if a pullup is detected when PERST is

deasserted. If a pulldown is detected, then the serial

IRQ interface is disabled.

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