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 2002 Semtech Corp.

www.semtech.com

POWER MANAGEMENT

SC1205H

PRELIMINARY

LAYOUT GUIDELINES

As with any high speed , high current, switching regulator

circuit, proper layout is critical in achieving optimum per-

formance of the SC1205H. The Evaluation board sche-

matic (Refer to figure 6) shows a two-phase synchronous

design with all surface mountable components.

Tight placement and short, wide traces must be used in

layout of The gate drives, DRN, and especially PGND pin.

The top gate driver supply voltage is provided by

bootstrapping the boost supply and adding it to the phase

node (DRN) voltage. Since the bootstrap capacitor sup-

plies the charge to the top gate, it must be less than .5”

away from the SC1205H. Ceramic X7R capacitors are a

good choice for supply bypassing near the chip.

Supply Voltage

The Vcc supply must be derived from a voltage that does

not vary significantly with output load. This is especially

true if the MOS.ET drain voltage is a +5V supply bus and

the Vcc of the SC1205H is connected to +5V. As the

load increases, or during sudden load transients, the 5V

supply dips significantly due to trace resistance and in-

ductance. If the Vcc of the SC1205H is derived from

the end of this +5V bus, the drop in the +5V can cause

the Vcc to fall lower than the required under voltage lock-

out threshold of the SC1205H and cause intermittent

drive shutdown. To avoid this occurrence, connect the

Vcc of the SC1205H to the beginning point of the +5V

bus with a separate trace, directly to the input connec-

tor.

The Vcc pin bypass capacitor must also be less than .5”

away from the SC1205H. The ground node of this ca-

pacitor, the SC1205H PGND pin and the Source of the

bottom .ET must be very close to each other, preferably

with common PCB copper land with multiple vias to the

ground plane (if used). The parallel Schottky (if used)

must be physically next to the Bottom .ET’s drain and

source pins. Any trace or lead inductance in these con-

nections will drive current way from the Schottky and

allow it to flow through the .ET’s Body diode, thus reduc-

ing efficiency.

Applications Information (Cont.)

Preventing Inadvertent Bottom .ET Turn-on

At high input voltages, (12V and greater) a fast turn-on

of the top .ET creates a positive going spike on the Bot-

tom .ET’s gate through the Miller capacitance, Crss of

the bottom .ET. The voltage appearing on the gate due

to this spike is:

Where Ciss is the input gate capacitance of the bottom

.ET. This is assuming that the impedance of the drive

path is too high compared to the instantaneous imped-

ance of the capacitors. (since dV/dT and thus the effec-

tive frequency is very high). If the BG pin of the SC1205H

is very close to the bottom .ET, Vspike will be reduced

depending on trace inductance, rate of rise of current,

etc.

While not shown in .igure 6, a capacitor may be added

from the gate of the Bottom .ET to its source, preferably

less than .5” away. This capacitor will be added to Ciss

in the above equation to reduce the effective spike volt-

age.

The bottom MOS.ET must be selected with attention

paid to the Crss/Ciss ratio. A low ratio reduces the Miller

feedback and thus reduces Vspike. Also MOS.ETs with

higher Turn-on threshold voltages will conduct at a higher

voltage and will not turn on during the spike. The MOS.ET

shown in the schematic (.igure 6) has a 2 volt threshold

and will require approximately 4.5 volts Vgs to be con-

ducting, thus reducing the possibility of shoot-through. A

zero ohm bottom .ET gate resistor will obviously help

keeping the gate voltage low during off time.

Ultimately, slowing down the top .ET by adding gate re-

sistance will reduce di/dt which will in turn make the ef-

fective impedance of the capacitors higher, thus allow-

ing the BG driver to hold the bottom gate voltage low. It

does this at the expense of increased switching times

(and switching losses) for the top .ET.

ciss

Crss

(

crss

*

Vin

V

SPIKE

+

=