SC4901ITSTRT datasheet(19/20 Pages) SEMTECH

19 / 20 page

 2005 Semtech Corp.

www.semtech.com

SC4901

POWER MANAGEMENT

OU T P UT 1

OU T P UT 2

OU T P UT N

QS1

DSN

QR1

DS1

DS2

QRN

QFN

QR2

DRN

QF1

QF2

DR2

QSN

••

DFN

QS2

DR1

DF1

DF2

GATE DRV2

GATE DRV1

GATE DRV N

Application Information (Cont.)

Features and Applications of the Combi Sync Circuit

with SC4901

The Combi Sync topology is quite versatile and has a

number of useful features

a) There is no connection between primary and secondary

sides. No synchronising signals, drive pulses, voltage or

current information needs to be exchanged across the

isolation boundary. The bias supply for the controller is

also generated on the secondary side, eliminating the

additional burden of a low power bias supply. SC4901 is

designed to operate over a range of 4.5V to 18V AVCC

supply which is the typical range for MOSFET gate drives.

b) For multiple secondary windings, each winding can have

its own set of synchronous MOSFETs and each set can be

controlled by an individual SC4901 to generate

independently regulated outputs. There is no cross

regulation or minimum load requirement, each output can

be turned ON or OFF independently of others. Placing the

controller on the secondary side also helps to optimise

the transient response.

c) It is possible to have multiple sets of synchronous FETs

attached to the same transformer secondary and control

them individually as shown in Fig 12. This way multiple

secondary outputs with a common ground can be regulated

off the same secondary winding.

d) All secondary switching is synchronised automatically

with the transformer waveform. There is only one switching

frequency in the convertor which simplifies EMI filter

design. Zero current switching of the primary FET further

reduces the switching noise generated on the primary side.

e) A number of options can be used to generate and control

the transformer secondary voltage.

i) The primary may be free running, that is without being

regulated by a feedback loop. It may further employ

constant volt second operation to reduce magnetic

stresses. In this mode the duty cycle is always at an

optimum value to maximise the efficiency.

ii) The primary may be regulated in a feedback loop by one

of the outputs; such regulation will typically employ voltage

mode or average current mode control. Note that peak

current mode control is not suitable with the trailing edge

modulation.

Fig 12) Generating Multiple Outputs from the same

secondary winding using Combi Sync Topology

f) It is necessary to drive the forward FETs through a

transformer interface. The common source of the two

devices is a floating return and will swing to the peak

negative voltage appearing at the transformer secondary;

see the Vsec waveform in Fig 11). This negative swing

does not allow a semiconductor device to be used for

driving the forward FET pair. An additional pin called XFRA

is provided in SC4901 to simplify the design of driver

transformer interface, particularly with duty ratios of >50%.

XFRA is an open collector sink which turns on and off

simultaneously with OUTA.

g) The no load condition at the output needs special

consideration in this topology. Under light load, the inductor

current is negative as in any synchronous rectifier. When

the synchronous MOSFET QR is turned off, the current is

interrupted and tends to charge the drain source capacitor

of QR. The back to back connected forward FETs prevent

this current being returned to the source. The resulting

overshoot on QR can be clamped by connecting a zener

and diode combination across the inductor as shown in

Fig 4). The zener clamp conducts only during the dead

time and also provides a small benefit of reducing the

voltage across the forward FETs during turn on. The detailed

application schematic in Fig 4) shows diode D1 and zener

D2 connected across the output inductor L1 to reduce the

no load spike.

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