SC4609 datasheet(7/18 Pages) SEMTECH

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SC4609

POWER MANAGEMENT

Application Information

Enable

The SC4609 is enabled by applying a voltage greater than

2.7 volts to the VCC pin. The SC4609 is disabled when

VCC falls below 2.35 volts or when sleep mode opera-

tion is invoked by clamping the FSET pin to a voltage

below 75mV. 10µA is the typical current drawn through

the VCC pin during sleep mode. During the sleep mode,

the high side and low side MOSFETs are turned off and

the internal soft start voltage is held low.

Oscillator

The FSET pin is used to set the PWM oscillator frequency

through an external timing capacitor that is connected

from the FSET pin to the GND pin. The resulting ramp

waveform ion the FSET pin is a triangle at the PWM fre-

quency with a peak voltage of 1.3V and a valley voltage

of 0.3V. 200ns minimum OFF time for the top switch

allows the bootstrap capacitor to be charged during each

cycle. The capacitor tolerance adds to the accuracy of

the oscillator frequency. The approximate operating fre-

quency and soft start time are both determined by the

value of the external timing capacitor as shown in Table

)

(

)

(

Table 1. Operating Frequency value Based on the

Value of the External Timing Capacitor Placed Across

the FSET and GND Pins

Synchronous mode operation is invoked by using a sig-

nal from an external clock. A low value resistor (100

Ω

typical) must be inserted in series with the timing capaci-

tor between the timing capacitor and the GND pin. The

other terminal of the timing capacitor will remain con-

nected to the FSET pin. The transformed external clock

signal is then connected to the junction of the external

timing capacitor and the added resistor R

SYNC as shown

in Figure 1.

The maximum frequency of the external clock signal can

be higher than the natural switching frequency by about

10%.

CFSET

RSYNC

100

SC4609

FSET

56pF

External

Clock

Signal

CFSET

RSYNC

100

SC4609

FSET

56pF

External

Clock

Signal

Figure 1

UVLO

When the FSET pin is not pulled and held below 75mV,

the voltage on the Vcc pin determines the operation of

the SC4609. As Vcc increases during start up, the UVLO

block senses Vcc and keeps the high side and low side

MOSFETs off and the internal soft start voltage low until

Vcc reaches 2.7V. If no faults are present, the SC4609

will initiate a soft start when Vcc exceeds 2.7V. A hyster-

esis (350mV) in the UVLO comparator provides noise

immunity during its start up.

Soft Start

The soft start function is required for step down control-

lers to prevent excess inrush current through the DC bus

during start up. Generally this can be done by sourcing a

controlled current into a timing capacitor and then using

the voltage across this capacitor to slowly ramp up the

error amp reference. The closed loop creates narrow

width driver pulses while the output voltage is low and

allows these pulses to increase to their steady state duty

cycle as the output voltage reaches its regulated value.

With this, the inrush current from the input side is con-

trolled. The duration of the soft start in the SC4609 is

controlled by an external capacitor. SS, the startup time

is difined as:

•

where, C is the value of the external capacitor in nF, and

SS is the startup time in second.

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