Pin Assignment

Pin Description

Pin Name

I/O

Options

Description

PA0~PA7

I/O

Pull-high

Wake-up

CMOS/Schmitt

Trigger Input

Bidirectional 8-bit input/output port. Software instructions determine the

CMOS output or Schmitt trigger input with pull-high resistor (determined by

pull-high options).

Each bit can be configured as a wake-up input by options.

PB0/BZ

PB1/BZ

PB2/INT

PB3/TMR

PB4~PB7

I/O

Pull-high

CMOS/Schmitt

PB0 or BZ

PB1 or BZ

Bidirectional 8-bit input/output port. Software instructions determine the

CMOS output or Schmitt trigger input with pull-high resistor (determined by

pull-high options).

The PB0 and PB1 are pin-shared with the BZ and BZ, respectively.

Once the PB0 or PB1 is selected as buzzer driving outputs, the output signal

This external interrupt input is pin-shared with PB2.The external interrupt in-

put is activated on a high to low transition. The timer input is pin-shared with

PB3.

PC0~PC7

I/O

Pull-high

PC0~PC7 constitute an 8-bit input/output port. PC0~PC7 are configured as

NMOS input/output pins with or without pull-high resistor by options.

PD0~PD7

I/O

Pull-high

PD0~PD7 constitute an 8-bit input/output port. PD0~PD7 are configured as

NMOS input/output pins with or without pull-high resistor by options.

PE0~PE7

I/O

Pull-high

PE0~PE7 constitute an 8-bit input/output port. PE0~PE7 are configured as

NMOS input/output pins with or without pull-high resistor by options.

RES

I

¾

Schmitt trigger reset input. Active low.

OSC1

I

RC

OSC1 is connected to an RC oscillator for the internal system clock.

OSC3

OSC4

I

O

RTC

Real time clock oscillators. OSC3 and OSC4 are connected to a 32768Hz

crystal oscillator for timing purposes.

TEST

I

¾

It is for test only. TEST pin is internally pull-high and can be left floating.

VDD

¾¾

Positive power supply

AVDD

¾¾

Positive power supply

VSS

¾¾

Negative Power supply, ground

AVSS

¾¾

Negative power supply, ground

PVSS0

¾¾

Negative power supply for PC, PD7~PD4 port, ground

PVSS1

¾¾

Negative power supply for PD3~PD0, PE port, ground

Note:

²*² The pull-high resistors of each I/O port (PA, PB, PC, PD, PE) are all controlled by port option.

HT48R52/HT48R53

Rev. 1.20

3

December 6, 2005

P A 7

P E 0

P E 1

P E 2

P E 3

P E 4

P E 5

P E 6

P E 7

P V S S 1

P D 0

P D 1

P D 2

V S S

P B 7

P B 6

P B 5

P B 4

P B 3 / T M R

P B 2 / I N T

P B 1 / B Z

P B 0 / B Z

A V D D

A V S S

N C

P C 7

1

2

3

4

5

6

7

8

9

1 0

1 1

1 2

1 3

1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2

3 4

3 5

3 6

3 7

3 8

3 9

4 8

4 9

5 0

5 1

5 2

2 3 2 4 2 5 2 6

2 7

2 8

2 9

3 0

3 1

3 2

3 3

H T 4 8 R 5 2 / H T 4 8 R 5 3

5 2 Q F P - A

4 0

4 1

4 2

4 3

4 4

4 5

4 6

4 7