HT46RB70 datasheet(13/53 Pages) HOLTEK

13 / 53 page

HT46RB70

Rev. 1.10

November 1, 2006

PDF

RESET Conditions

RES reset during power-up

RES reset during normal operation

RES wake-up at HALT

WDT time-out during normal operation

WDT wake-up at HALT

Note:

²u² stands for ²unchanged²

To guarantee that the system oscillator is started and

stabilized, the SST (System Start-up Timer) provides an

extra-delay of 1024 system clock pulses when the sys-

tem awakes from the HALT state or during power up.

Awaking from the HALT state or system power up, an

SST delay is added. An extra SST delay is added during

power up period, and any wake-up from HALT may en-

able only the SST delay. The functional unit chip reset

status are shown below.

Program Counter

000H

Interrupt

Disable

Prescaler, Divider

Cleared

WDT

Clear. After master reset,

WDT begins counting

Timer/event Counter

Off

Input/output Ports

Input mode

Stack Pointer

Points to the top of the stack

W a r m R e s e t

W D T

H A L T

C o l d

R e s e t

R E S

P o w e r - o n D e t e c t i o n

S S T

1 0 - b i t R i p p l e

C o u n t e r

O S C 1

W D T

E x t e r n a l

T i m e - o u t

R e s e t

Reset Configuration

t S S T + t O P D

R E S

V D D

S S T T i m e - o u t

C h i p R e s e t

Reset Timing Chart

R E S

V D D

1 0 0 k W

1 0 k W

0 . 1 m F *

0 . 0 1 m F *

Reset Circuit

Note:

²*² Make the length of the wiring, which is con-

nected to the RES pin as short as possible, to

avoid noise interference.

The registers states are summarized in the following table.

Reset

(Power On)

WDT

Time-out

(Normal

Operation)

RES Reset

(Normal

Operation)

RES Reset

(HALT)

WDT

Time-out

(HALT)*

USB Reset

(Normal)

USB Reset

(HALT)

TMR0H

xxxx xxxx

uuuu uuuu

xxxx xxxx

TMR0L

xxxx xxxx

uuuu uuuu

xxxx xxxx

TMR0C

00-0 1000

uu-u uuuu

00-0 1000

TMR1H

xxxx xxxx

uuuu uuuu

xxxx xxxx

TMR1L

xxxx xxxx

uuuu uuuu

xxxx xxxx

TMR1C

00-0 1---

uu-u u---

00-0 1---

Program

Counter

000H

MP0

xxxx xxxx

uuuu uuuu

MP1

xxxx xxxx

uuuu uuuu

ACC

xxxx xxxx

uuuu uuuu

TBLP

xxxx xxxx

uuuu uuuu

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