10

 2004 Semtech Corp.

www.semtech.com

SC4611

POWER MANAGEMENT

3.3V/10A Evaluation Board Schematic

U1

SC4611ITSTR

PVCC

VOUT

C3

C8

C9

C17

10 uF

C19

10 uF

C21

N/U

C4

C10

C14

C15

10 nF

R4

.01R/1W

R1

1R

R3

N/U

R6

2R

R8

2R

1K

R9

5R

R10

10K

VGG

R11

R12

10K

R13

1K

R26

33.2K

R21

10K

R23

1.78K

R17

20K

R19

2K

R18

10R

R25

10R

J1

J2

J3

J4

PH

D3

N/U

D1

VIN

GDL

GDH

RTN

C5

RTN

C6

C7

VDC

C1

L1

SHORT

C2

AVCC

TP1

TP3

TP4

TP11

TP10

TP9

TP7

TP6

C13

1 nF

TP2

TP5

R2

3.3V

CLM

Q1

6612

Q2

N/U

Q3

6670

Q4

6670

EAO

R5

.01R/1W

OVP

10-15V Vin to 3.3V/10A 300 kHz Reference Design With SC4611

J5-2

R22

249R

J5-3

J5-4

C12

2.2 nF

J5-1

J6-2

J6-1

J6-3

J6-4

+S

N/U

N/U

TP12

TP13

C11

1 uF

CS-

CS+

TP14

TP15

SS

TP8

D2

RED

R7

1K

RTN

RTN

VOUT

Q5

3906

C16

100 uF

C18

100 uF

VFB

C20

N/U

-S

BST

2). The high power, high current parts of the circuit should

be laid out first. The on time loop formed by the input

capacitor Cin, the high side FET Q

the output capacitor bank Cout must be kept as small as

possible. Another loop area to minimise is formed by low

side FET Q

bank Cout during the off period. These loops contain all

the high current, fast transition switching. Connections

should be as wide and as short as possible to minimize

loop inductance.

3). The connection between the junction of Q

output inductor should be a wide trace or copper region. It

should be as short as practical. Since this connection has

fast voltage transitions, keeping this connection short will

minimize EMI. Also keep the Phase connection to the IC

short. The top FET gate charge currents flow in this trace.

4) The output capacitor Cout should be located as close to

the load terminals as possible. Fast transient load currents

are supplied by Cout and connections between Cout and

the load must be kept short with wide copper areas to

minimize inductance and resistance. This will improve the

transient response to step loads.

5) The SC4611 is best placed over a quiet ground plane

area. Avoid pulse currents of the Cin, Q

this area. This analog ground plane should be connected

to the power ground plane at a “quiet” point near the input

capacitor. Under no circumstance should it be returned to

a point inside the Cin, Q

6) The SC4611 AGND pin is connected to the separate

analog ground plane with minimum lead length . All analog

grounding paths including decoupling capacitors, feedback

resistors, compensation components, and current-limit

setting resistors should be connected to the same plane.

Applications Information (Cont.)