6

www.semtech.com

POWER MANAGEMENT

SC1104A/B

Synchronous Buck Converter

The output voltage of the synchronous converter is set

and controlled by the output of the error amplifier. The

inverting input of the error amplifier receives its voltage

from the SENSE pin. The non-inverting input of the error

amplifier is connected to an internal 1V reference.

The error amplifier output is connected to the

COMPensation pin. The error amplifier generates a cur-

rent proportional to (Vsense – 1V), which is the COMP

pin output current (Transconductance ~ 12mS).

The

voltage on the COMP pin is the integral of the error am-

plifier current. The COMP voltage is the non-inverting

input to the PWM comparator and controls the duty cycle

of the MOSFET drivers. The size of capacitor Ccomp con-

trols the stability and transient response of the regula-

tor. The larger the capacitor, the slower the COMP volt-

age changes, and the slower the duty cycle changes.

The inverting input voltage of the PWM comparator is

the triangular output of the oscillator.

When the oscillator output voltage drops below the COMP

voltage, the comparator output goes high. This pulls DL

low, turning off the low-side FET. After a short delay (“dead

time”), DH is pulled high, turning on the high-side FET.

When the oscillator voltage rises back above the error

amplifier output voltage, the comparator output goes low.

This pulls DH low, turning off the high-side FET, and after

a dead time delay, DL is pulled high, turning on the low-

side FET. The dead time delay is determined by a

monostable on the chip.

The triangle wave minimum is about 1V, and the maxi-

mum is about 2V. Thus, if Vcomp = 0.9V, high side duty

cycle is the minimum (~0%) , but if Vcomp is 2.0V, duty

cycle is at maximum ( ~90%).The internal oscillator uses

an on-chip capacitor and trimmed precision current

sources to set the oscillation frequency to 300kHz

(SC1104A) or 600kHz (SC1104B).

Figure 1 shows a 3.3V output converter. If the Vout <3.3V,

then the SENSE voltage < 1V. In this case the error

amplifier will be sourcing current into the COMP pin so

that COMP voltage and duty cycle will gradually increase.

If Vout > 3.3V, the error amplifier will sink current and

reduce the COMP voltage, so that duty cycle will decrease.

The circuit will be in steady state when Vout =3.3V ,

Vsense = 1V, Icomp = 0 . The COMP voltage and duty

cycle depend on Vin.

Under Voltage Lockout

The under voltage lockout circuit of the SC1104A/B as-

sures that both high-side and low-side MOSFET driver

outputs remain in the off state whenever the supply volt-

age drops below set parameters. Lockout occurs if V

CC

falls below 4.2V typ.

R

In case of a short circuit or overload, the high-side (HS)

FET will conduct large currents. To prevent damage, in

this situation, large currents will generate a fault condi-

tion and begin a soft start cycle.

While the HS driver is on, the phase voltage is compared

to the Vcc pin voltage. If the phase voltage is 200mV

lower than Vcc, a fault is latched and the soft start cycle

begins.

The voltages are compared during the middle of the HS

pulse, to prevent transients from affecting the accuracy.

The sampling of the voltage across the top FET occurs

after a time delay t

DH is pulled high. This delay prevents the measurement

to be effected by ringing on the leading edge of the phase

node pulse. The duration of the sampling is t

100ns_typ. It is being disabled at very low duty cycle when

t

up during the inrush of the current charging output ca-

pacitor and the fault free operation with extremely high

input/output voltage ratio, e.g., V

The over-current comparator (OC) is only active if the

phase node is > 3.3V. This means that in the case of

power source being < 3V the OC will be disabled even

though the rest of the circuitry is completely functional.

SC1104 still can be used for stepping down, e.g. 2.8V to

2.5V, 2V, 1.8V, etc.

Theory of Operation