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SC1405D

POWER MANAGEMENT

placement and short, wide traces must be used in layout

of The Drives, DRN, and especially PGND pin. The top

gate driver supply voltage is provided by bootstrapping

the +5V supply and adding it the phase node voltage

(DRN). Since the bootstrap capacitor supplies the charge

to the TOP gate, it must be less than 0.5” away from the

SC1405. Ceramic X7R capacitors are a good choice for

supply bypassing near the chip. The Vcc pin capacitor

must also be less than 0.5” away from the SC1405. The

ground node of this capacitor, the SC1405 PGND pin

and the Source of the bottom FET must be very close to

each other, preferably with common PCB copper land

and multiple vias to the ground plane (if used). The par-

allel Schottky (if used) must be physically next to the

Bottom FET’s drain and source. Any trace or lead induc-

tance in these connections will drive current way from

the Schottky and allow it to flow through the FET’s body

diode, thus reducing efficiency.

Preventing Inadvertent Bottom FET Turn-on

At high input voltages, (12V and greater) a fast turn-on

of the top FET creates a positive going spike on the Bot-

tom FET’s gate through the Miller capacitance, Crss of

the bottom FET. The voltage appearing on the gate due

to this spike is:

iss

rss

rss

in

spike

C

C

C

*

V

V

+

=

Where Ciss is the input gate capacitance of the bottom

FET. This is assuming that the impedance of the drive

path is too high compared to the instantaneous imped-

ance of the capacitors. (since dV/dT and thus the effec-

tive frequency is very high). If the BG pin of the SC1405D

is very close to the bottom FET, Vspike will be reduced

depending on trace inductance, rate if rise of current,

etc.

While not shown in Application Evaluation Board Sche-

matic on page 12, a capacitor may be added from the

gate of the bottom FET to its source, preferably less than

0.5” away. This capacitor will be added to Ciss in the

above equation to reduce the effective spike voltage,

Vspike.

The selection of the bottom FET must be done with at-

tention paid to the Crss/Ciss ratio. A low ratio reduces

Applications Information

the Miller feedback and thus reduces Vspike. Also FETs

with higher Turn-on threshold voltages will conduct at a

higher voltage and will not turn on during the spike. The

FET shown in the schematic has a 2 volt threshold and

will require approximately 5 volts Vgs to be conducting,

thus reducing the possibility of shoot-through. A zero

ohm bottom FET gate resistor will obviously help keeping

the gate voltage low.

Ultimately, slowing down the top FET by adding gate re-

sistance will reduce di/dt which will in turn make the ef-

fective impedance of the capacitors higher, thus allow-

ing the BG driver to hold the bottom gate voltage low.

Ringing on the Phase Node

The top FET source must be close to the bottom FET

drain to prevent ringing and the possibility of the phase

node going negative.

This frequency is determined by:

oss

st

ring

C

*

L

2

1

F

Π

=

Where:

L

to trace inductance of the connection between top FET’s

source and the bottom FET’s drain added to the trace

resistance of the bottom FET’s ground connection.

Coss=Drain to source capacitance of bottom FET. If there

is a Schottky used, the capacitance of the Schottky is

added to the value.

Although this ringing does not pose any power losses

due to a fairly high Q, it could cause the phase node to

go too far negative, thus causing improper operation,

double pulsing or at worst driver damage. This ringing is

also an EMI nuisance due to its high resonant frequency.

Adding a capacitor, typically 1000-2000pf, in parallel with

Coss can often eliminate the EMI issue. If double puls-

ing is caused due to excessive ringing, placing 4.7-10

ohm resistor between the phase node and the DRN pin

of the SC1405 should eliminate the double pulsing.

The negative voltage spikes on the phase node adds to

the bootstrap capacitor voltage, thus increasing the volt-

age between VBST - VDRN. If the phase node negative

spikes are too large, the voltage on the boost capacitor