SC1109BSTR datasheet(8/19 Pages) SEMTECH

8 / 19 page

 2004 Semtech Corp.

www.semtech.com

POWER MANAGEMENT

SC1109

The internal charge pump charges an external Bucket

capacitor to VSTBY and then connects it in series with

VSTBY to the LDOs supply at a frequency of about

200kHz. This ensures sufficient gate drive voltage for

the LDOs independent of the VCC or the 12V external

supply being available due to start up timing sequence

from the silver box.

The LDO1, and LDO2 output voltages are forced to track

the 3.3V input supply. This feature ensures that during

the start up application of the 3.3V, the LDO1, and LDO2

outputs track the 3.3V within 200mV typical until regula-

tion is achieved. However, the VSTBY should be established

at least 500us, to allow the charge pump to reach its

maximum voltage, before the linear section will track within

200mV. This tracking will sequence the correct start up

timing for the external Chipset and Clock circuitry.

LAYOUT GUIDELINES

Careful attention to layout requirements are necessary

for successful implementation of the SC1109 PWM con-

troller. High currents switching are present in the appli-

cation and their effect on ground plane voltage differen-

tials must be understood and minimized.

1). The high power parts of the circuit should be laid out

first. A ground plane should be used, the number and

position of ground plane interruptions should be such as

to not unnecessarily compromise ground plane integrity.

Isolated or semi-isolated areas of the ground plane may

be deliberately introduced to constrain ground currents

to particular areas, for example the input capacitor and

bottom FET ground.

2). The loop formed by the Input Capacitor(s) (Cin), the

Top FET (Q1) and the Bottom FET (Q2) must be kept as

small as possible. This loop contains all the high current,

fast transition switching. Connections should be as wide

and as short as possible to minimize loop inductance.

Minimizing this loop area will a) reduce EMI, b) lower

ground injection currents, resulting in electrically “cleaner”

grounds for the rest of the system and c) minimize source

ringing, resulting in more reliable gate switching signals.

3). The connection between the junction of Q1, Q2 and

the output inductor should be a wide trace or copper

region. It should be as short as practical. Since this con-

nection has fast voltage transitions, keeping this con-

nection short will minimize EMI. Also keep the Phase con-

nection to the IC short, top FET gate charge currents

flow in this trace.

1.5V

1.8V

3.3V IN

C10

330uF

VTT

5V IN

SC1109A

PWRGD

BCAP-

STBY

PHASE

GND

BST

VOSENSE

SS/EN

BCAP+

VCC

GATE2

GATE1

LDOS1

LDOS2

5V STBY

12V IN

high current paths.

Heavy Lines indicate

Application Information (Cont.)

3.3V Vin

1.8V Vout

1.5V Vout

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