HT36A4 datasheet(13/38 Pages) HOLTEK

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HT36A4

Rev. 1.10

March 12, 2007

Reset

There are 3 ways in which a reset can occur:

· RES reset during normal operation

· RES reset during HALT

· WDT time-out reset during normal operation

The WDT time-out during HALT is different from other

chip reset conditions, since it can perform a

²warm re -

set

² that just resets the program counter and stack

pointer, leaving the other circuits to maintain their state.

Some registers remain unchanged during any other re-

set conditions. Most registers are reset to the

²initial

condition

² when the reset conditions are met. By exam-

ining the PDF and TO flags, the program can distinguish

between different

²chip resets².

PDF

RESET Conditions

RES reset during power-up

RES reset during normal operation

RES wake-up HALT

WDT time-out during normal operation

WDT wake-up HALT

Note:

²u² stands for unchanged

To guarantee that the system oscillator has started and

stabilized, the SST (System Start-up Timer) provides an

extra-delay of 1024 system clock pulses during system

power up or when the system awakes from a HALT

state.

When a system power-up occurs, the SST delay is

added during the reset period. But when the reset co-

mes from the RES pin, the SST delay is disabled. Any

wake-up from HALT will enable the SST delay.

The functional units chip reset status are shown below.

Program Counter

000H

Interrupt

Disable

Prescaler

Clear

WDT

Clear. After master reset,

WDT begins counting

Timer Counter (0/1)

Off

Input/output ports

Input mode

Stack Pointer

Points to the top of stack

t S S T

R E S

V D D

S S T T i m e - o u t

C h i p R e s e t

Reset Timing Chart

W D T

H A L T

W D T

T i m e - o u t

R e s e t

R E S

C o l d

R e s e t

W a r m R e s e t

P o w e r - o n D e t e c t i n g

S S T

1 0 - s t a g e

R i p p l e C o u n t e r

O S C I

Reset Configuration

R E S

V D D

Reset Circuit

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