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405GP датащи(PDF) 52 Page - Applied Micro Circuits Corporation

номер детали 405GP
подробное описание детали  Power PC 405GP Embedded Processor
PDF  59 Pages
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производитель  AMCC [Applied Micro Circuits Corporation]
домашняя страница  http://www.amcc.com
Logo AMCC - Applied Micro Circuits Corporation

405GP датащи(HTML) 52 Page - Applied Micro Circuits Corporation

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405GP – Power PC 405GP Embedded Processor
52
AMCC
Revision 2.03 – September 7, 2007
Data Sheet
Internal Peripheral Interface
IICSCL
na
na
nana1912
IICSDA
na
na
nana1912
UART0_CTS
na
na
12
8
UART0_DCD
na
na
12
8
UART0_DSR
na
na
12
8
UART0_DTR
12
8
UART0_RI
na
na
12
8
UART0_RTS
na
na
12
8
UART0_Rx
na
na
12
8
UART0_Tx
na
na
12
8
UART1_RTS/
UART1_DTR
na
na
12
8
UART1_DSR/
UART1_CTS
na
na
na
na
UART1_Rx
na
na
na
na
UART1_Tx
na
na
12
8
UARTSerClk
na
na
na
na
Interrupts Interface
IRQ0:6[GPIO17:23]
12
8
JTAG Interface
TCK
na
na
async
TDI
na
na
async
TDO
12
8
async
TMS
na
na
async
TRST
na
na
async
System Interface
DrvrInh1:2
dc
dc
nananana
GPIO1[TS1E]
GPIO2[TS2E]
GPIO3[TS1O]
GPIO4[TS2O]
GPIO5[TS3]
GPIO6[TS4]
GPIO7[TS5]
GPIO8[TS6]
GPIO9[TrcClk]
12
8
Halt
dc
dc
na
na
na
na
async
RcvrInh
dc
dc
nananana
SysClk
na
na
na
na
SysErr
na
na
12
8
async
SysReset
101128
async
TestEn
dc
dc
na
na
na
na
async
TmrClk
dc
dc
na
na
na
na
async
I/O Specifications—All speeds (Part 2 of 2)
Notes:
1. PCI timings are for operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for 33.33MHz.
In synchronous mode, timing is relative to SysClk. In asynchronous mode, timing is relative to PCIClk.
2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
3. For PCI, I/O H is specified at 0.9OVDD and I/O L is specified at 0.1OVDD. For all other interfaces, I/O H is specified at 2.4 V
and I/O L is specified at 0.4 V.
Signal
Input (ns)
Output (ns)
Output Current (mA)
Clock
Notes
Setup Time
(TIS min)
Hold Time
(TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(min)
I/O L
(min)



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