S5935QF datasheet(39/204 Pages) AMCC

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S5935 – PCI Product

Revision 1.02 – June 27, 2006

AMCC Confidential and Proprietary

DS1527

Data Book

Table 8. PCI Status Register

Bit

Description

Detected Parity Error. This bit is set whenever a parity error is detected. It functions independently from the state of

Command Register Bit 6. This bit may be cleared by writing a 1 to this location.

Signaled System Error. This bit is set whenever the device asserts the signal SERR#. This bit can be reset by writing

a 1 to this location.

Received Master Abort. This bit is set whenever a bus master abort occurs. This bit can be reset by writing a 1 to this

location.

Received Target Abort. This bit is set whenever this device has one of its own initiated cycles terminated by the cur-

rently addressed target. This bit can be reset by writing a 1 to this location.

Signaled Target Abort. This bit is set whenever this device aborts a cycle when addressed as a target. This bit can be

reset by writing a 1 to this location.

10:9

Device Select Timing. These bits are read-only and define the signal behavior of DEVSEL# from this device when

accessed as a target.

Data Parity Reported. This bit is set upon the detection of a data parity error for a transfer involving the S5935 device

as the master. The Parity Error Enable bit (D6 of the Command Register) must be set in order for this bit to be set.

Once set, it can only be cleared by either writing a 1 to this location or by the assertion of the signal RESET#.

Fast Back-to-back Capable. When equal to 1, this indicates that the device can accept fast back-to-back cycles as a

target.

6:0

Reserved. Equal all 0’s.

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