TAS5352 datasheet(21/27 Pages) TI

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Overcurrent (OC) Protection With Current

Pin-To-Pin Short Circuit Protection (PPSC)

TAS5352

SLES204 – SEPTEMBER 2007

voltage on the bootstrap capacitors is less than

In general, it is recommended to follow closely the

required

for

proper

control

the

High-Side

external component selection and PCB layout as

MOSFETs, the device will initiate bootstrap capacitor

given in the Application section.

recharge sequences until the bootstrap capacitors are

For

added

flexibility,

the

threshold

properly charged for robust operation. This function

programmable within a limited range using a single

may be activated with PWM pulses less than 30 nS.

external resistor connected between the OC_ADJ pin

Therefore, TI strongly recommends using a TI PWM

and AGND. (See the Electrical Characteristics section

processor, such as TAS5518, TAS5086 or TAS5508,

of this data sheet for information on the correlation

with the modulation index set at 97.7% to interface

between programming-resistor value and the OC

with TAS5352.

threshold.) It should be noted that a properly

functioning

overcurrent

detector

assumes

the

presence of a properly designed demodulation filter at

Limiting and Overload Detection

the power-stage output. It is required to follow certain

guidelines when selecting the OC threshold and an

The device has independent, fast-reacting current

appropriate demodulation inductor:

detectors with programmable trip threshold (OC

OC-Adjust Resistor Values

Max. Current Before OC Occurs

threshold) on all high-side and low-side power-stage

Ω)

(A), TC = 75°C

FETs. See the following table for OC-adjust resistor

10.9

values. The detector outputs are closely monitored by

two protection systems. The first protection system

9.1

controls the power stage in order to prevent the

7.1

output current from further increasing, i.e., it performs

a current-limiting function rather than prematurely

The reported max peak current in the table above is

shutting down during combinations of high-level

measured with continuous current in 1

Ω, one

music

transients

and

extreme

speaker

load

channel active and the other one muted.

impedance

drops.

the

high-current

situation

persists, i.e., the power stage is being overloaded, a

second

protection

system

triggers

latching

The PPSC detection system protects the device from

shutdown, resulting in the power stage being set in

permanent damage in the case that a power output

the high-impedance (Hi-Z) state. Current limiting and

pin (OUT_X) is shorted to GND_X or PVDD_X. For

overload protection are independent for half-bridges

comparison the OC protection system detects an over

A and B and, respectively, C and D. That is, if the

current after the demodulation filter where PPSC

bridge-tied load between half-bridges A and B causes

detects shorts directly at the pin before the filter.

an overload fault, only half-bridges A and B are shut

PPSC detection is performed at startup i.e. when

down.

VDD is supplied, consequently a short to either

• For the lowest-cost bill of materials in terms of

GND_X or PVDD_X after system startup will not

component selection, the OC threshold measure

activate the PPSC detection system. When PPSC

should be limited, considering the power output

detection is activated by a short on the output, all half

requirement

and

minimum

load

impedance.

bridges are kept in a Hi-Z state until the short is

Higher-impedance loads require a lower OC

removed, the device then continues the startup

threshold.

sequence and starts switching. The detection is

• The demodulation-filter inductor must retain at

controlled globally by a two step sequence. The first

least 5

μH of inductance at twice the OC threshold

step ensures that there are no shorts from OUT_X to

setting.

GND_X, the second step tests that there are no

shorts from OUT_X to PVDD_X. The total duration of

Unfortunately,

most

inductors

have

decreasing

this process is roughly proportional to the capacitance

inductance

with

increasing

temperature

and

of the output LC filter. The typical duration is < 15

increasing current (saturation). To some degree, an

ms/

μF. While the PPSC detection is in progress, SD

increase

temperature

naturally

occurs

when

is kept low, and the device will not react to changes

operating at high output currents, due to core losses

applied to the RESET pins. If no shorts are present

and the dc resistance of the inductor's copper

the PPSC detection passes, and SD is released. A

winding. A thorough analysis of inductor saturation

device reset will not start a new PPSC detection.

and thermal properties is strongly recommended.

PPSC detection is enabled in BTL and PBTL output

Setting the OC threshold too low might cause issues

configurations, the detection is not performed in SE

such

lack

enough

output

power

and/or

mode. To make sure not to trip the PPSC detection

unexpected shutdowns due to too-sensitive overload

system it is recommended not to insert resistive load

detection.

to GND_X or PVDD_X.

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