MCP2155 datasheet(11/40 Pages) MICROCHIP

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DS20001894D-page 11

MCP2122

2.6

Host UART Interface

The UART interface is used to communicate with the

Host Controller. Though a UART is capable of a full-

duplex interface, the direct coupling to the IR encoder/

decoder allows only half-duplex operation (since the IR

side is either receiving or transmitting and not both at

the same time). This means that the system can’t

transmit and receive at the same time.

2.6.1

TRANSMITTING

When the controller sends serial data to the MCP2122,

the baud rates are required to match.

There will be some jitter on the detection of the high-to-

low edge of the start bit. This jitter will affect the place-

ment of the encoded start bit. All subsequent bits will be

16 BITCLK times later.

While RXIR is receiving data (low pulse), the TXIR pin

is disabled from transmitting.

2.6.2

RECEIVING

When the controller receives serial data from the

MCP2122, the baud rates are required to match.

There will be some jitter on the detection of the high-to-

low edge of the Start bit. This jitter will affect the

placement of the decoded Start bit. All subsequent bits

will be 16 BITCLK times later.

The TXIR pin is disabled when data is being received

(low pulse) on the RXIR pin.

2.7

IR Interface

The IR interface is used to communicate with the

optical receiver circuitry. The IR interface is either

transmitting data or receiving data (half-duplex).

2.8

Encoding/Decoding Jitter and

Offset

Figure 2-11 shows the jitter on the RXIR and TX pins,

along with the offset on the RX pin and the TXIR pin.

Jitter is the possible variation of the desired edge.

Figure 2-9 and Figure 2-10 show the jitter of the TX pin

(range is indicated by red dashed lines).

Offset is the propagation delay of the input signal (RXIR

or TX) to the output signal (RX or TXIR). Figure 2-9 and

Figure 2-10 show the offset of the TXIR pin from the

16XCLK signal that starts the bit time.

2.9

Minimizing Power

The device can be placed in a low-power mode by

forcing the RESET pin low. This disables the internal

state machine. To ensure that the lowest power

consumption is obtained, ensure that the 16XCLK pin

is not active and that the other input pins (TX and RXIR)

are at a logic-high or logic-low level.

2.9.1

RETURNING TO OPERATION

When returning to normal operation, the RESET pin

must be forced high and the 16XCLK signal should be

operating. Time should be given to ensure that the

16XCLK is stabilized at the desired frequency before

data is allowed to be transmitted or received.

FIGURE 2-11:

EFFECTS OF JITTER AND OFFSET

TX Jitter

3 16XCLK

BITCLK

RXIR

TXIR

16 16XCLK

3 16XCLK

16 16XCLK

RX Jitter

TX Offset

RX Offset

16 16XCLK

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