MCP1630-ESLASHMS datasheet(12/30 Pages) MICROCHIP

12 / 30 page

MCP1630/MCP1630V

DS20001896D-page 12

 2004-2022 Microchip Technology Inc. and its subsidiaries

4.0

DETAILED DESCRIPTION

4.1

Device Overview

The MCP1630 is comprised of a high-speed

comparator, high-bandwidth amplifier and logic gates

that can be combined with a PIC MCU to develop an

advanced programmable power supply. The oscillator

and reference voltage inputs are generated by the PIC

MCU so that switching frequency, maximum duty cycle

and output voltage are programmable. Refer to

Figure 4-1.

4.2

PWM

The VEXT output of the MCP1630/V is determined by

the output level of the internal high-speed comparator

and the level of the external oscillator. When the

oscillator level is high, the PWM output (VEXT) is forced

low. When the external oscillator is low, the PWM

output is determined by the output level of the internal

high-speed comparator. During UVLO, the VEXT pin is

held in the low state. During overtemperature

operation, the VEXT pin is high-impedance (100 k to

ground).

4.3

Normal Cycle by Cycle Control

The beginning of a cycle is defined when OSC IN

transitions from a high state to a low state. For normal

operation, the state of the high-speed comparator

output (R) is low and the Q output of the latch is low. On

the OSC IN high-to-low transition, the S and R inputs to

the high-speed latch are both low and the Q output will

remain unchanged (low). The output of the OR gate

(VDRIVE) will transition from a high state to a low state,

turning on the internal P-channel drive transistor in the

output stage of the PWM. This will change the PWM

output (VEXT) from a low state to a high state, turning

on the power-train external switch and ramping current

in the power-train magnetic device.

The sensed current in the magnetic device is fed into

the CS input (shown as a ramp) and increases linearly.

Once the sensed current ramp (MCP1630) reaches the

same voltage level as 1/3 of the EA output, the

comparator output (R) changes states (low-to-high)

and resets the PWM latch. The Q output transitions

from a low state to a high state, turning on the N-

channel MOSFET in the output stage, which turns off

the VEXT drive to the external MOSFET driver

terminating the duty cycle. The OSC IN will transition

from a low state to a high state while the VEXT pin

remains unchanged. If the CS input ramp had never

reached the same level as 1/3 of the error amplifier

output, the low-to-high transition on OSC IN would

terminate the duty cycle and this would be considered

maximum duty cycle. In either case, while OSC IN is

high, the VEXT drive pin is low, turning off the external

power-train switch. The next cycle will start on the

transition of the OSC IN pin from a high state to a low

state.

For Voltage mode or Average Current mode

applications that utilize a large signal ramp at the CS

input, the MCP1630V is used to provide more signal

(2.7V typ.). The operation of the PWM does not

change.

4.4

Error Amp/Comparator Current

Limit Function

The internal amplifier is used to create an error output

signal that is determined by the external VREF input and

the power supply output fed back into the FB pin. The

error amplifier output is rail-to-rail and clamped by a

precision 2.7V. The output of the error amplifier is then

divided down 3:1 (MCP1630) and connected to the

inverting input of the high-speed comparator. Since the

maximum output of the error amplifier is 2.7V, the

maximum input to the inverting pin of the high-speed

comparator is 0.9V. This sets the peak current limit for

the switching power supply.

For the MCP1630V, the maximum error amplifier

output is still 2.7V. However, the resistor divider is

removed, raising the maximum input signal level at the

high-speed comparator inverting input (CS) to 2.7V.

As the output load current demand increases, the error

amplifier output increases, causing the inverting input

pin of the high-speed comparator to increase.

Eventually, the output of the error amplifier will hit the

2.7V clamp, limiting the input of the high-speed

comparator to 0.9V max (MCP1630). Even if the FB

input continues to decrease (calling for more current),

the inverting input is limited to 0.9V. By limiting the

inverting input to 0.9V, the current-sense input (CS) is

limited to 0.9V, thus limiting the output current of the

power supply.

For Voltage mode control, the error amplifier output will

increase as input voltage decreases. A voltage ramp is

used instead of sensed inductor current at the CS input

of the MCP1630V. The 3:1 internal error amplifier

output resistor divider is removed in the MCP1630V

option to increase the maximum signal level input to

2.7V (typ.).

4.5

0% Duty Cycle Operation

The duty cycle of the VEXT output is capable of

reaching 0% when the FB pin is held higher than the

VREF pin (inverting error amplifier). This is

accomplished by the rail-to-rail output capability of the

error amplifier and the offset voltage of the high-speed

comparator. The minimum error amplifier output

voltage, divided by three, is less than the offset voltage

of the high-speed comparator. In the case where the

output voltage of the converter is above the desired

regulation point, the FB input will be above the VREF

input and the error amplifier will be pulled to the bottom

rail (GND). This low voltage is divided down 3:1 by the

2R and 1R resistor (MCP1630) and connected to the

input of the high-speed comparator. This voltage will be

low enough so that there is no triggering of the

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