Nexperia

PHDMI2FS4

Extremely low capacitance unidirectional ESD protection diode array

5. Pinning information

Table 2. Pinning information

Pin

Symbol

Description

Simplified outline

Graphic symbol

1

CH1

channel 1 ESD protection

2

CH2

channel 2 ESD protection

3

GND

ground

4

CH3

channel 3 ESD protection

5

CH4

channel 4 ESD protection

6

n.c.

not connected

7

n.c.

not connected

8

GND

ground

9

n.c.

not connected

10

n.c.

not connected

Transparent top view

10 9

8

7

6

1

2

3

4

5

DFN2510A-10 (SOT1176-2)

CH1

CH2

CH3

CH4

GND

=

aaa-016329

6. Ordering information

Table 3. Ordering information

Package

Type number

Name

Description

Version

PHDMI2FS4

DFN2510A-10 plastic, extremely thin small outline package; no leads; 10

terminals; body 1.0 x 2.5 x 0.5 mm

SOT1176-2

7. Application information

The device is designed for the protection of four unidirectional data or signal lines from surge

pulses and ESD damage.

The device uses an advanced clamping structure showing a negative dynamic resistance.

This snap-back behavior strongly reduces the clamping voltage to the system behind the ESD

protection during an ESD event. Do not connect unlimited DC current sources to the data lines to

avoid keeping the ESD protection device in snap-back state after exceeding breakdown voltage

(due to an ESD pulse for instance).

Circuit board layout and protection device placement

Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT) and surge

transients. The following guidelines are recommended:

1. Place the device as close to the input terminal or connector as possible.

2. Minimize the path length between the device and the protected line.

3. Keep parallel signal paths to a minimum.

4. Avoid running protected conductors in parallel with unprotected conductors.

5. Minimize all Printed-Circuit Board (PCB) conductive loops including power and ground loops.

6. Minimize the length of the transient return path to ground.

7. Avoid using shared transient return paths to a common ground point.

8. Use ground planes whenever possible. For multilayer PCBs, use ground vias.

PHDMI2FS4_SDS

All information provided in this document is subject to legal disclaimers.

©

Nexperia B.V. 2024. All rights reserved

Short data sheet

27 September 2024

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