| поискавой системы для электроныых деталей |
|
SC16C2550B датащи(PDF) 21 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
SC16C2550B датащи(HTML) 21 Page - NXP Semiconductors |
|
21 / 43 page ![]() SC16C2550B_4 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 04 — 15 February 2007 21 of 43 NXP Semiconductors SC16C2550B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 7.6 Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. Table 16. LCR[2] stop bit length LCR[2] Word length (bits) Stop bit length (bit times) 0 5, 6, 7, 8 1 15 11 ⁄ 2 1 6, 7, 8 2 Table 17. LCR[1:0] word length LCR[1] LCR[0] Word length (bits) 005 016 107 118 Table 18. Modem Control Register bits description Bit Symbol Description 7:5 MCR[7:5] reserved; set to ‘0’ 4 MCR[4] Loop-back. Enable the local Loop-back mode (diagnostics). In this mode the transmitter output (TX) and the receiver input (RX), CTS, DSR, CD and RI are disconnected from the SC16C2550B I/O pins. Internally the modem data and control pins are connected into a loop-back data configuration (see Figure 7). In this mode, the receiver and transmitter interrupts remain fully operational. The Modem Control Interrupts are also operational, but the interrupts’ sources are switched to the lower four bits of the Modem Control. Interrupts continue to be controlled by the IER register. logic 0 = disable Loop-back mode (normal default condition) logic 1 = enable local Loop-back mode (diagnostics) 3 MCR[3] OP2/INT enable logic 0 = forces INT (A, B) outputs to the 3-state mode and sets OP2 to a logic 1 (normal default condition) logic 1 = forces the INT (A, B outputs to the active mode and sets OP2 to a logic 0 2 MCR[2] (OP1). OP1A/OP1B are not available as an external signal in the SC16C2550B. This bit is instead used in the Loop-back mode only. In the Loop-back mode, this bit is used to write the state of the modem RI interface signal. 1 MCR[1] RTS logic 0 = force RTS output to a logic 1 (normal default condition) logic 1 = force RTS output to a logic 0 0 MCR[0] DTR logic 0 = force DTR output to a logic 1 (normal default condition) logic 1 = force DTR output to a logic 0 |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |