R2023K datasheet(39/50 Pages) RICOH

39 / 50 page

R2023K/T

Alarm and Periodic Interrupt

The R2023K/T incorporates the alarm interrupt circuit and the periodic interrupt circuit that are configured to

generate alarm signals and periodic interrupt signals for output from the INTRA or INTRB pin as described

below.

(1) Alarm Interrupt Circuit

The alarm interrupt circuit is configured to generate alarm signals for output from the INTRA or INTRB , which

is driven low (enabled) upon the occurrence of a match between current time read by the time counters (the

day-of-week, hour, and minute counters) and alarm time preset by the alarm registers (the Alarm_W registers

intended for the day-of-week, hour, and minute digit settings and the Alarm_D registers intended for the hour and

minute digit settings).

The Alarm_W is output from the INTRB pin, the Alarm_D is output from INTRA pin.

(2) Periodic Interrupt Circuit

The periodic interrupt circuit is configured to generate either clock pulses in the pulse mode or interrupt signals in

the level mode for output from the INTRA pin depending on the CT2, CT1, and CT0 bit settings in the control

The above two types of interrupt signals are monitored by the flag bits (i.e. the WAFG, DAFG, and CTFG bits in the

Control Register 2) and enabled or disabled by the enable bits (i.e. the WALE, DALE, CT2, CT1, and CT0 bits in

the Control Register 1) as listed in the table below.

Flag bits

Enable bits

Output Pin

Alarm_W

WAFG

(D1 at Address

Fh)

WALE

(D7 at Address Eh)

INTRB

Alarm_D

DAFG

(D0 at Address

Fh)

DALE

(D6 at Address Eh)

INTRA

Peridic

interrupt

CTFG

(D2 at Address

Fh)

CT2=CT1=CT0=0

(These bit setting of “0” disable the Periodic

nterrupt)

(D2 to D0 at Address Eh)

INTRA

At power-on, when the WALE, DALE, CT2, CT1, and CT0 bits are set to 0 in the Control Register 1,

the INTRA or INTRB pin is driven high (disabled).

When two types of interrupt signals are output simultaneously from the INTRA pin, the output from the

INTRA pin becomes an OR waveform of their negative logic.

Example: Combined Output to INTRA Pin Under Control of

ALARM_D and Periodic Interrupt

Periodic Interrupt

INTRA

Alarm_D

In this event, which type of interrupt signal is output from the INTRA pin can be confirmed by reading the

DAFG, and CTFG bit settings in the Control Register 2.

• Alarm Interrupt

The alarm interrupt circuit is controlled by the enable bits (i.e. the WALE and DALE bits in the Control Register 1)

and the flag bits (i.e. the WAFG and DAFG bits in the Control Register 2).

The enable bits can be used to enable

R2023K датащи(PDF) 39 Page - RICOH electronics devices division

R2023K датащи(HTML) 39 Page - RICOH electronics devices division

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

датащи скачать

ссылки URL