SN54LS490, SN74LS490

DUAL 4-BIT DECADE COUNTERS

SDLS125A – OCTOBER 1976 – REVISED JULY 1998

8

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

tPHL

tPLH

tPLH

tPHL

LOAD CIRCUIT

FOR 3-STATE OUTPUTS

1.3 V

1.3 V

High-Level

Pulse

Low-Level

Pulse

tw

VOLTAGE WAVEFORMS

PULSE DURATIONS

Input

Out-of-Phase

Output

(see Note F)

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

3 V

0 V

VOL

VOH

VOH

VOL

In-Phase

Output

(see Note F)

1.3 V

1.3 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VCC

RL

Test

Point

From Output

Under Test

CL

(see Note A)

LOAD CIRCUIT

FOR OPEN-COLLECTOR OUTPUTS

LOAD CIRCUIT FOR

BI-STATE

TOTEM-POLE OUTPUTS

(see Note B)

VCC

RL

From Output

Under Test

CL

(see Note A)

Test

Point

(see Note B)

VCC

RL

From Output

Under Test

CL

(see Note A)

Test

Point

5 k

Ω

NOTES: A. CL includes probe and jig capacitance.

B. All diodes are 1N3064 or equivalent.

C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

D. In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily.

E. All input pulses are supplied by generators having the following characteristics: PRR

≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 15 ns, tf ≤ 6 ns.

F. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.

G. The outputs are measured one at a time with one input transition per measurement.

S1

S2

tPHZ

tPLZ

tPZL

tPZH

1.3 V

1.3 V

1.3 V

3 V

3 V

0 V

0 V

th

tsu

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Timing

Input

Data

Input

1.3 V

1.3 V

1.3 V

1.3 V

3 V

0 V

Output

Control

(low-level

enabling)

Waveform 1

S2 Open

(see Notes C

and F)

Waveform 2

S2 Closed

(see Notes C

and F)

[1.5 V

VOH – 0.3 V

VOL + 0.3 V

[1.5 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

Figure 2. Load Circuits and Voltage Waveforms