CS42L51 datasheet(49/88 Pages) CIRRUS

49 / 88 page

DS679F1

CS42L51

6. REGISTER DESCRIPTION

All registers are read/write except for the chip I.D. and Revision Register and Interrupt Status Register which are

read only. See the following bit definition tables for bit assignment information. The default state of each bit after a

power-up sequence or reset is listed in each bit description.

All “Reserved” registers must maintain their default state.

Note:

Certain functions are only available when the “Signal Processing Engine to DAC” option is selected using

the DATA_SEL[1:0] bits, as described in section “DAC Data Selection (DATA_SEL[1:0])” on page 58.

6.1

Chip I.D. and Revision Register (Address 01h) (Read Only)

Chip I.D. (Chip_ID[4:0])

Default: 11011

Function:

I.D. code for the CS42L51. Permanently set to 11011.

Chip Revision (Rev_ID[2:0])

Default: 001

Function:

CS42L51 revision level. Revision B is coded as 001. Revision A is coded as 000.

6.2

Power Control 1 (Address 02h)

Notes:

To activate the power-down sequence for individual channels (A or B,) both channels must first be pow-

ered down either by enabling the PDN bit or by enabling the power-down bits for both channels. En-

abling the power-down bit on an individual channel basis after the CODEC has fully powered up will

mute the selected channel without achieving any power savings.

Recommended channel power-down sequence: 1.) Enable the PDN bit, 2.) enable power-down for the se-

lect channels, 3.) disable the PDN bit.

Power Down DAC X (PDN_DACX)

Default: 0

0 - Disable

1 - Enable

Function:

DAC channel x will either enter a power-down or muted state when this bit is enabled. See Note 1 above.

432

Chip_ID4

Chip_ID3

Chip_ID2

Chip_ID1

Chip_ID0

Rev_ID2

Rev_ID1

Rev_ID0

432

Reserved

PDN_DACB

PDN_DACA

PDN_PGAB

PDN_PGAA

PDN_ADCB

PDN_ADCA

PDN

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