®

AS7C4098A

2/21/06, v 1.2

Alliance Semiconductor

P. 7 of 11

AC test conditions

Notes

2

For test conditions, see AC Test Conditions, Figures A and B.

4

This parameter is guaranteed, but not tested.

5WE is High for read cycle.

6CE and OE are Low for read cycle.

7

Address valid prior to or coincident with CE transition Low.

8

All read cycle timings are referenced from the last valid address to the first transitioning address.

9

All write cycle timings are referenced from the last valid address to the first transitioning address.

10 C = 30 pF, except on High Z and Low Z parameters, where C = 5 pF.

Address

CE

LB, UB

WE

Data undefined

High Z

High Z

Data valid

- Output load: see Figure B.

- Input rise and fall times: 2 ns. See Figure A.

- Input and output timing reference levels: 1.5V.

10%

90%

10%

90%

GND

2 ns

Figure A: Input pulse

255

Ω

480

Ω

GND

+5.0V

Figure B:5.0V Output load

168

Ω

+1.728V

Thevenin equivalent: