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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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UCS1002-3 датащи(PDF) 30 Page - Microchip Technology |
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UCS1002-3 датащи(HTML) 30 Page - Microchip Technology |
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30 / 114 page  UCS1002-3 DS20006852A-page 30 2023 Microchip Technology Inc. and its subsidiaries 6.0 USB HIGH-SPEED DATA SWITCH The UCS1002-3 contains a series USB 2.0-compliant high-speed switch between the DPIN and DMIN pins and between the DPOUT and DMOUT pins. This switch is designed for high-speed, low-latency functionality to enable USB 2.0 full-speed and high- speed communications with minimal interference. Nominally, the switch is closed in the Active state, enabling uninterrupted USB communications between the upstream host and the portable device. The switch is opened when: • The UCS1002-3 is actively emulating using any of the charger emulation profiles except CDP (by default - see Section 10.4.5 “High-Speed Switch Configuration Register”). • The UCS1002-3 is operating as a dedicated charger unless the HSW_DCE configuration bit is set (see Section 10.4.5 “High-Speed Switch Configuration Register”). • The UCS1002-3 is in the Detect state (by default) or in the Sleep state. 6.1 USB-IF High-Speed Compliance The USB data switch does not significantly degrade the signal integrity through the device DP/DM pins with USB high-speed communications. Note: If the VDD voltage is less than VDD_TH, the high-speed data switch is disabled and opened. |
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