MIC2132YML datasheet(20/48 Pages) MICROCHIP

20 / 48 page

MIC2132

DS20006654B-page 20

 2022 Microchip Technology Inc. and its subsidiaries

4.2

Start-up Into Pre-Bias Load

To get proper pre-bias start-up performance, the voltage

at the junction of CINJ and RINJ needs to be at its

steady-state value when the device starts switching. This

is done by biasing the RIP_INJ pin voltage using a

current source (IBIAS) at the RIP_INJ pin and a resistor

(RBIAS) at the RIP_INJ pin before the device starts

switching. The Injection (INJ) driver will be in

High-Impedance mode before the device starts switch-

ing. This results in a voltage equal to IBIAS x RBIAS at the

RIP_INJ pin before switching starts. This voltage charges

the CINJ cap to the value of IBIAS x RBIAS. As the CINJ

takes time to charge to the final voltage, depending on

the CINJ x (RINJ + RFB(BOT)), the IBIAS must be enabled

before the switching starts. The MIC2132 has a POK

delay of ≈4 ms (i.e., when EN is high, the device starts

switching after ≈4 ms). Therefore, this 4 ms delay is

enough to charge CINJ to the final value. Once the device

starts switching, the IBIAS will no longer have any effect,

as the ripple injection driver will be either high or low (the

ripple injection driver will not be in High-Impedance mode

when the device starts switching).

FIGURE 4-4:

Circuit to Obtain Proper

Pre-Bias Start-up Performance and Ripple

Injection.

IBIAS is an internal current source. RBIAS is an external

resistor from RIP_INJ to AGND. RBIAS can be

calculated using the formula below:

EQUATION 4-3:

Note that as RBIAS is always present, it draws an

additional current from the INJ driver when the RIP_INJ

pin is 5V for 100 ns. This adds to the device’s IQ.

However, its contribution to the device’s IQ will be low

because this current will be present for 100 ns only.

Another thing to note is that the INJ driver must be

capable of supplying this additional current.

4.3

Stability Analysis

The MIC2132 uses ripple-based constant on-time

architecture to generate switching pulses. The magni-

tude of the ripple needs to be in the range of 20 mV to

100 mV. In order to avoid ripple voltage variation with

input voltage, ripple voltage is injected from the third

node through the RIP_INJ pin. Figure 4-5 shows the

ripple injection at the FBS node with respect to the

reference voltage.

FIGURE 4-5:

MIC2132 Ripple Injection at

FBS Node.

The

output

capacitors

generally

have

three

components. The capacitive ripple lags the inductor

current ripple. The ESR ripple is in phase with the

inductor current. The ESL ripple effect is minimal in

low-voltage capacitors.

AGND

st DH

DETECTION

100 ns

1-SHOT PULSE

VDD

INJECTION

DRIVER

LOGIC

INJ_ON

RIP_INJ

FBS

IBIAS

VDD

RINJ

CNJ

FEED FORWARD

0.6V

GFB

CFF

VOUT

RBIAS

MIC2132

RFB(TOP)

RFB(BOT)

1.2V

VREF_COM

VREF

Where:

5V × 100 ns × fSW = Average Voltage on the RIP_INJ Pin

RBIAS =

5V × 100 ns × fSW

IBIAS

CONTROL

LOGIC

ON TIM

TIME

GEN

GENER

ERA

ATIO

TION

HSD

LSD

VIN

VREF (0.6V)

FEEDFORWARD

Vgm

VREF_COM

Fixed O Time

Cycle starts when

VREF_COM = Vgm

RIPPLE

INJECTION

DRIVER

Vgm

FBS

GFB

VOUT

RFB(TOP)

RFB(BOT)

COM

RSA

RINJ

CINJ

CFF

VREF_COM (1.2V)

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