PCA9674ABS datasheet(21/34 Pages) PHILIPS

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PCA9674_PCA9674A_2

Product data sheet

Rev. 02 — 12 October 2006

21 of 34

NXP Semiconductors

PCA9674/74A

Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt

13. Dynamic characteristics

[1]

tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.

[2]

tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.

[3]

Cb = total capacitance of one bus line in pF.

[4]

A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to

bridge the undeﬁned region SCL’s falling edge.

[5]

The maximum tf for the SDA and SCL bus lines is speciﬁed at 300 ns. The maximum fall time for the SDA output stage tf is speciﬁed at

250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without

exceeding the maximum speciﬁed tf.

[6]

Input ﬁlters on the SDA and SCL inputs suppress noise spikes less than 50 ns.

Table 9.

Dynamic characteristics

VDD = 2.3 V to 5.5 V; VSS =0V; Tamb = −40 °Cto+85 °C; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Standard mode

I2C-bus

Fast mode I2C-bus

Fast-mode Plus

I2C-bus

Unit

Min

Max

Min

Max

Min

Max

fSCL

SCL clock frequency

100

400

1000

kHz

tBUF

bus free time between a

STOP and START condition

4.7

1.3

0.5

µs

tHD;STA

hold time (repeated) START

condition

4.0

0.6

0.26

µs

tSU;STA

set-up time for a repeated

START condition

4.7

0.6

0.26

µs

tSU;STO

set-up time for STOP

condition

4.0

0.6

0.26

µs

tHD;DAT

data hold time

tVD;ACK

data valid acknowledge

time[1]

0.3

3.45

0.1

0.9

0.05

0.45

µs

tVD;DAT

data valid time[2]

300

450

tSU;DAT

data set-up time

250

100

tLOW

LOW period of the SCL clock

4.7

1.3

0.5

µs

tHIGH

HIGH period of the SCL

clock

4.0

0.6

0.26

µs

fall time of both SDA and

SCL signals

[4][5]

300

20 + 0.1Cb[3]

300

120

rise time of both SDA and

SCL signals

1000

20 + 0.1Cb[3]

300

120

tSP

pulse width of spikes that

must be suppressed by the

input ﬁlter[6]

Port timing; CL ≤ 100 pF (see Figure 14 and Figure 15)

tv(Q)

data output valid time

µs

tsu(D)

data input setup time

µs

th(D)

data input hold time

µs

Interrupt timing; CL ≤ 100 pF (see Figure 14 and Figure 15)

tv(D)

data input valid time

µs

td(rst)

reset delay time

µs

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