CYIS1SM0250-AA
Document Number: 38-05713 Rev. *B
Page 17 of 24
80
TRI_ADC
Tri-state control of digital ADC outputs
1 = tri-state; 0 = output
Table 11. Digital Output Signals
Pin
Pin Name
Pin Description
23
EOS_YL
End-of-scan of YL shift register.
Low first clock period after last row (low active).
26
EOS_X
End-of-scan of X shift register.
Low first clock period after last active column (low active).
29
EOS_YR
End-of-scan of YR shift register.
Low first clock period after last row (low active).
55
D0
ADC output bit (LSB).
56
D1
ADC output bit.
57
D2
ADC output bit.
58
D3
ADC output bit.
59
D4
ADC output bit.
60
D5
ADC output bit.
61
D6
ADC output bit.
62
D7
ADC output bit.
63
D8
ADC output bit.
64
D9
ADC output bit (MSB).
Table 12. Analog Input Signals
Pin
Pin Name
Pin Description
39
NBIASARR
Connect with 470 k to Vdd and decouple to ground with a 100 nF capacitor.
40
PBIAS
Connect with 39 k to ground and decouple to Vdd with a 100 nF capacitor for 8 MHz
pixel rate. (Lower resistor values yield higher maximal pixel rates at the cost of extra
power dissipation).
41
NBIAS_AMP
Output amplifier speed/power control.
Connect with 51k
Ω to VDD and decouple with 100 nF to GND for 8 MHz output rate
(Lower resistor values yield higher maximal pixel rates at the cost of extra power
dissipation).
42
BLACKREF
Control voltage for output signal offset level.
Buffered on-chip, the reference level can be generated by a 100k
Ω resistive divider.
Connect to +/- 2 V DC for use with on-chip ADC.
44
IN_ADC
Input, connect to sensor's output.
Input range is between 2 & 4 V (VLOW_ADC & VHIGH_ADC).
45
NBIASANA2
Connect with 100 k to VDD and decouple to GND.
46
NBIASANA
Connect with 100 k to VDD and decouple to GND.
47
70
VLOW_ADC
VHIGH_ADC
Low reference and high reference voltages of ADC should be about 2 and 4V.
The required voltage settings on VLOW_ADC and VHIGH_ADC can be approximated
by tying VLOW_ADC with 1.2k
Ω to GND and VHIGH_ADC with 560Ω to VDD.
Table 10. Digital Input Signals (continued)
Pin
Pin Name
Pin Description
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