I/O

Control

Interface

SCL

SDA

Temperature

Register

Configuration

Register

T

LOW

Register

T

HIGH

Register

Pointer

Register

TMP175-Q1, TMP75-Q1

SBOS759 – NOVEMBER 2015

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7.5 Programming

7.5.1 Pointer Register

Figure 11 shows the internal register structure of the TMP175-Q1 and TMP75-Q1. The 8-bit Pointer register of

the devices is used to address a given data register. The Pointer register uses the two LSBs to identify which of

the data registers must respond to a read or write command. Table 4 identifies the bits of the Pointer register

byte. Table 5 describes the pointer address of the registers available in the TMP175-Q1 and TMP75-Q1. The

power-up reset value of P1/P0 is 00.

Figure 11. Internal Register Structure of the TMP175-Q1 and TMP75-Q1

Table 4. Pointer Register Byte (pointer = N/A) [reset = 00h]

P7

P6

P5

P4

P3

P2

P1

P0

0

0

0

0

0

0

Register Bits

Table 5. Pointer Addresses of the TMP175-Q1 and TMP75-Q1

P1

P0

TYPE

REGISTER

0

0

R only, default

Temperature register

0

1

R/W

Configuration register

1

0

R/W

TLOW register

1

1

R/W

THIGH register

16

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