ST10F269ZX datasheet(174/184 Pages) STMICROELECTRONICS

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ST10F269

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21.4.14 - High-Speed Synchronous Serial Interface (SSC) Timing

21.4.14.1 Master Mode

VCC = 5V ±10%, VSS = 0V, CPU clock = 40MHz, TA = -40 to +125°C, CL = 50pF (PQFP144 devices)

Note: 1. Timing guaranteed by design.

The formula for SSC Clock Cycle time is: t300 = 4 TCL * (<SSCBR> + 1)

Where <SSCBR> represents the content of the SSC Baud rate register, taken as unsigned 16-bit integer.

VCC = 5V ±10%, VSS = 0V, CPU clock = 32MHz, TA = -40 to +125°C, CL = 50pF (TQFP144 devices)

Symbol

Parameter

Maximum Baud rate = 10M Baud

(<SSCBR> = 0001h)

Variable Baud rate

(<SSCBR>=0001h-FFFFh)

Unit

Minimum

Maximum

Minimum

Maximum

t300

CC SSC clock cycle time

100

8 TCL

262144 TCL

t301

CC SSC clock high time

–

t300/2 - 10

–ns

t302

CC SSC clock low time

–

t300/2 - 10

–ns

t303

CC SSC clock rise time

–

t304

CC SSC clock fall time

–

t305

CC Write data valid after shift edge

–

t306

CC Write data hold after shift edge 1

-2

–

-2

–

t307p SR Read data setup time before

latch edge, phase error

detection on (SSCPEN = 1)

37.5

–

2TCL+12.5

–

t308p SR Read data hold time after latch

edge, phase error detection on

(SSCPEN = 1)

–

4TCL

–

t307

SR Read data setup time before

latch edge, phase error

detection off (SSCPEN = 0)

–

2TCL

–

t308

SR Read data hold time after latch

edge, phase error detection off

(SSCPEN = 0)

0–

–

Symbol

Parameter

Maximum Baud rate=6.25MBd

(<SSCBR> = 0001h)

Variable Baud rate

(<SSCBR>=0001h-FFFFh) Symb

Minimum

Maximum

Minimum

Maximum

t310 SR SSC clock cycle time

125

–

8 TCL

262144 TCL

t310

t311 SR SSC clock high time

52.5

–

t310/2 - 10

–

t311

t312 SR SSC clock low time

52.5

–

t310/2 - 10

–

t312

t313 SR SSC clock rise time

–

t313

t314 SR SSC clock fall time

–

t314

t315 CC Write data valid after shift edge

–

45.25

–

2 TCL + 14

t315

t316 CC Write data hold after shift edge

–

t316

t317p SR Read data setup time before latch edge,

phase error detection on (SSCPEN = 1)

78.125

–

4TCL +

15.625

–

t317p

t318p

SR Read data hold time after latch edge,

phase error detection on (SSCPEN = 1)

109.375

–

6TCL +

15.625

–

t318p

t317 SR Read data setup time before latch edge,

phase error detection off (SSCPEN = 0)

6–

–

t317

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