ST10F269ZX datasheet(162/184 Pages) STMICROELECTRONICS

162 / 184 page

ST10F269

162/184

t81

Address/Unlatched CS setup

to RD, WR

(no RW-delay)

5.625 + 2tA

–TCL -10 + 2tA

–ns

t12

RD, WR low time

(with RW-delay)

21.25 + tC

–

2TCL - 10 + tC

–ns

t13

RD, WR low time

(no RW-delay)

36.875 + tC

–

3TCL - 10 + tC

–ns

t14

RD to valid data in

(with RW-delay)

–

11.25 + tC

–

2TCL - 20 + tC

t15

RD to valid data in

(no RW-delay)

–

26.875 + tC

–

3TCL - 20 + tC

t16

ALE low to valid data in

–

26.875 + tA +

–3TCL - 20

+ tA + tC

t17

Address/Unlatched CS to

valid data in

–

32.5 + 2tA +

–

4TCL - 30

+ 2tA + tC

t18

Data hold after RD

rising edge

0–

–

t20

Data float after RD rising

edge (with RW-delay)1 - 3

–

26 + tF

–

2TCL - 14

+ tF + 2tA

t21

Data float after RD rising

edge (no RW-delay) 1 - 3

–

5.625 + tF

–TCL - 10

+ tF + 2tA

t22

Data valid to WR

11.25 + tC

–

2TCL- 20 + tC

–ns

t24

Data hold after WR

5.625 + tF

–TCL - 10+ tF

–ns

t26

ALE rising edge after RD, WR

-10 + tF

–

-10 + tF

–ns

t28

Address/Unlatched CS hold

after RD, WR 2

0 (no tF)

-5 + tF

(tF > 0)

–

0 (no tF)

-5 + tF

(tF > 0)

–ns

t28h

Address/Unlatched CS hold

after WRH

-5 + tF

–-5 + tF

–ns

t38

ALE falling edge to Latched

-4 - tA

10 - tA

-4 - tA

10 - tA

t39

Latched CS low to Valid Data

–

26.875 + tC+

2tA

–

3TCL - 20

+ tC + 2tA

t41

Latched CS hold after RD,

1.625 + tF

–TCL - 14 + tF

–ns

t82

Address setup to RdCS,

WrCS

(with RW-delay)

17.25 + 2tA

–

2TCL - 14 + 2tA

–ns

t83

Address setup to RdCS,

WrCS

(no RW-delay)

1.625 + 2tA

–TCL -14 + 2tA

–ns

t46

RdCS to Valid Data In

(with RW-delay)

–

7.25 + tC

–

2TCL - 24 + tC

t47

RdCS to Valid Data In

(no RW-delay)

–

22.875 + tC

–

3TCL - 24 + tC

Symbol

Parameter

Maximum CPU Clock =

32MHz

Variable CPU Clock

1/2 TCL = 1 to 32MHz

Unit

Minimum

Maximum

Minimum

Maximum

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