ST10F269ZX datasheet(161/184 Pages) STMICROELECTRONICS

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ST10F269

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Notes: 1. RW-delay and

A refer to the next following bus cycle.

2. Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address

changes before the end of RD have no impact on read cycles.

3. Partially tested, guaranteed by design characterization.

VDD = 5V ± 10%, VSS = 0V, TA = -40 to +85°C, CL = 50pF,

ALE cycle time = 4 TCL + 2tA + tC + tF (125ns at 32MHz CPU clock without wait states) RW-delay and tA

refer to the next following bus cycle.

Table 49 : Demultiplexed Bus Characteristics (TQFP144 devices)

t41 CC

Latched CS hold after RD, WR

2 + tF

–

TCL - 10.5 + tF

–ns

t82 CC

Address setup to RdCS, WrCS

(with RW-delay)

14.5 + 2tA

–

2 TCL - 10.5 +

2tA

–ns

t83 CC Address setup to RdCS, WrCS

(no RW-delay)

2 + 2tA

–

TCL - 10.5 + 2tA

–ns

t46 SR

RdCS to Valid Data In

(with RW-delay)

–4 + tC

–

2 TCL - 21 + tC

t47 SR

RdCS to Valid Data In

(no RW-delay)

–

16.5 + tC

–

3 TCL - 21 + tC

t48 CC

RdCS, WrCS Low Time

(with RW-delay)

15.5 + tC

–2 TCL - 9.5

+ tC

–ns

t49 CC RdCS, WrCS Low Time

(no RW-delay)

28 + tC

–

3 TCL - 9.5 + tC

–ns

t50 CC Data valid to WrCS

10 + tC

–

2 TCL - 15 + tC

–ns

t51 SR

Data hold after RdCS

0–

–

t53 SR

Data float after RdCS

(with RW-delay)

–

16.5 + tF

–

2 TCL - 8.5 + tF

t68 SR

Data float after RdCS

(no RW-delay)

–4 + tF

–

TCL - 8.5 + tF

t55 CC

Address hold after

RdCS, WrCS

-8.5 + tF

–

-8.5 + tF

–ns

t57 CC

Data hold after WrCS

2 + tF

–

TCL - 10.5 + tF

–ns

Table 48 : Demultiplexed Bus Characteristics (PQFP144 devices)

Symbol

Parameter

Maximum CPU Clock

= 40MHz

Variable CPU Clock

1/2 TCL = 1 to 40MHz

Minimum

Maximum

Minimum

Maximum

Symbol

Parameter

Maximum CPU Clock =

32MHz

Variable CPU Clock

1/2 TCL = 1 to 32MHz

Unit

Minimum

Maximum

Minimum

Maximum

ALE high time

5.625 + tA

–TCL - 10+ tA

–ns

Address setup to ALE

0.625 + tA

–TCL - 15+ tA

–ns

t80

Address/Unlatched CS setup

to RD, WR

(with RW-delay)

21.25 + 2tA

–

2TCL - 10 + 2tA

–ns

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