2.5V or 3.3V, 200-MHz, 1:12 Clock
Distribution Buffer
CY29948
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 38-07288 Rev. *C
Revised February 16, 2006
Features
• 2.5V or 3.3V operation
• 200-MHz clock support
• LVPECL or LVCMOS/LVTTL clock input
• LVCMOS-/LVTTL-compatible inputs
• 12 clock outputs: drive up to 24 clock lines
• Synchronous Output Enable
• Output three-state control
• 150 ps typical output-to-output skew
• Pin compatible with MPC948, MPC948L, MPC9448
• Available in Commercial and Industrial temp. range
• 32-pin TQFP package
Description
The CY29948 is a low-voltage 200-MHz clock distribution
buffer with the capability to select either a differential LVPECL
or a LVCMOS/LVTTL compatible input clock. The two clock
sources can be used to provide for a test clock as well as the
primary
system
clock.
All
other
control
inputs
are
LVCMOS/LVTTL compatible. The 12 outputs are LVCMOS or
LVTTL compatible and can drive 50
Ω series or parallel termi-
nated transmission lines. For series terminated transmission
lines, each output can drive one or two traces giving the device
an effective fanout of 1:24. The outputs can also be
three-stated
via
the
three-state
input
TS#.
Low
output-to-output skews make the CY29948 an ideal clock
distribution buffer for nested clock trees in the most
demanding of synchronous systems.
The CY29948 also provides a synchronous output enable
input for enabling or disabling the output clocks. Since this
input is internally synchronized to the input clock, potential
output glitching or runt pulse generation is eliminated.
Block Diagram
Pin Configuration
PECL_CLK
PECL_CLK#
0
1
TCLK
TCLK_SEL
SYNC_OE
TS#
VDD
VDDC
12
Q0-Q11
CY29948
VSS
Q4
VDDC
Q5
VSS
Q6
VDDC
Q7
TCLK_SEL
TCLK
PECL_CLK
PECL_CLK#
SYNC_OE
TS#
VDD
VSS
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
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