CS5560

DS713A5

29

7/31/07

VREF+, VREF- – Voltage Reference Input, Pin 9, 10

A differential voltage reference input on these pins functions as the voltage reference for the

converter. The voltage between these pins can range between 2.4 volts and 4.2 volts, with

4.096 volts being the nominal reference voltage value.

BP/UP – Bipolar/Unipolar Select, Pin 11

The BP/UP pin determines the span and the output coding of the converter. When set high to

select BP (bipolar), the input span of the converter is -4.096 volts to +4.096 volts fully differential

(assuming the voltage reference is 4.096 volts) and outputs data is coded in two's complement

format. When set low to select UP (unipolar), the input span is 0 to +4.096 fully differential and

the output data is coded in binary format.

SLEEP – Sleep Mode Select, Pin 12

When taken low, the SLEEP pin will cause the converter to enter into a low-power state. SLEEP

will stop the internal oscillator and power down all internal analog circuitry.

RST – Reset, Pin 13

Reset is necessary after power is initially applied to the converter. When the RST input is taken

low, the logic in the converter will be reset. When RST is released to go high, certain portions of

the analog circuitry are started. RDY falls when reset is complete.

CAL – Calibrate, Pin 14

After power is applied, a reset should be performed prior to calibration. After an initial reset, cal-

ibration can be performed at any time. Calibration can be initiated in either of two ways. If CAL

is high when coming out of reset, (RST going high), a calibration will be performed. If RST is

taken high with CAL low, a calibration is not performed, but calibration can be initiated by taking

CAL high at any time the converter is idle. RDY will also fall when calibration is completed.

CONV – Convert, Pin 15

The CONV pin initiates a conversion cycle if taken low, unless a calibration cycle or a previous

conversion is in progress. When the conversion cycle is completed, the conversion word is out-

put to the serial port register and the RDY signal goes low. If CONV is held low and remains low

when RDY falls another conversion cycle will be started.

DCR – Digital Core Regulator, Pin 16

DCR is the output of the on-chip regulator for the digital logic core. DCR should be bypassed

with a capacitor to V2-. The DCR pin is not designed to power any external load.

V2+ – Positive Power 2, Pin 17

The V1+ and V2+ pins provide a positive supply voltage to the circuitry of the chip. These two

pins should be decoupled as shown in the application block diagrams. V1+ and V2+ should be

supplied from the same source voltage. For single supply operation these two voltages are

nominally +5 V. For dual supply operation they are nominally +2.5 V.

V2- – Negative Power 2, Pin 18

The V1- and V2- pins provide a negative supply voltage to the circuitry of the chip. These two

pins should be decoupled as shown in the application block diagrams. V1- and V2- should be

supplied from the same source voltage. For single supply operation these two voltages are

nominally 0 V (Ground). For dual supply operation they are nominally -2.5 V.

MCLK – Master Clock, Pin 19

The master clock pin (MCLK) is a multi-function pin. If tied low (MCLK = VLR) the on-chip oscil-

lator will be enabled. If tied high (MCLK = VL), all clocks to the internal circuitry of the converter

will stop. When MCLK is held high the internal oscillator will also be stopped. MCLK can also

function as the input for an external CMOS-compatible clock that conforms to supply voltages

on the VL and VLR pins.