P4C168, P4C169, P4C170

Page 4 of 15

Document # SRAM107 REV A

Notes:

7. ADDRESS must be valid prior to, or coincident with CE/CS transition

low. For Fast CS, t

8. Transition is measured ±200mV from steady state voltage prior to

change, with loading as specified in Figure 1.

9. Read Cycle Time is measured from the last valid address to the first

transitioning address.

TIMING WAVEFORM OF READ CYCLE NO. 2 (CE

CE

CE

CE

CE/CS

CS

CS

CS

TIMING WAVEFORM OF READ CYCLE NO. 3—P4C170 ONLY (OE

OE

OE

OE

Notes:

5. WE is HIGH for READ cycle.

6. CE/CS and OE are LOW for READ cycle.