P4C167

Page 6 of 10

Document # SRAM106 REV A

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE

CE

CE

CE

Figure 1. Output Load

Figure 2. Thevenin Equivalent

* including scope and test fixture.

Note:

Due to the ultra-high speed of the P4C167/L, care must be taken when

testing this device; an inadequate setup can cause a normal functioning

part to be rejected as faulty. Long high-inductance leads that cause

supply bounce must be avoided by bringing the V

directly up to the contactor fingers. A 0.01 µF high frequency capacitor

is also required between V

proper termination must be used; for example, a 50

Ω test environment

should be terminated into a 50

Ω load with 1.73V (Thevenin Voltage) at

the comparator input, and a 116

Ω resistor must be used in series with

D

AC TEST CONDITIONS

TRUTH TABLE

Input Pulse Levels

GND to 3.0V

Input Rise and Fall Times

3ns

Input Timing Reference Level

1.5V

Output Timing Reference Level

1.5V

Output Load

See Figures 1 and 2

Mode

CE

CE

CE

CE

CE

WE

WE

WE

WE

WE

Output

Power

Standby

H

X

High Z

Standby

Read

L

H

D

OUT

Active

Write

L

L

High Z

Active