PCA9502_3

© NXP B.V. 2006. All rights reserved.

Product data sheet

Rev. 03 — 13 October 2006

15 of 25

NXP Semiconductors

PCA9502

[1]

5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 3.8 V steady state voltage

tolerance on inputs and outputs when no supply voltage is present.

13. Dynamic characteristics

[1]

may be ordered using the code 9398 393 40011.

[2]

Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if SDA is held LOW for a

minimum of 25 ms.

HIGH-level input voltage

1.6

5.5[1]

2.0

5.5[1]

V

LOW-level input voltage

-

0.6

-

0.8

V

leakage current

-10-10

µA

input capacitance

-7-7

pF

Table 15.

Symbol

Parameter

Conditions

Unit

Min

Max

Min

Max

Table 16.

All the timing limits are valid within the operating supply voltage, ambient temperature range and output load;

All output load = 25 pF, except SDA output load = 400 pF.[1]

Symbol Parameter

Conditions

Standard-mode

Fast-mode

Unit

Min

Max

Min

Max

SCL clock frequency

[2]

0

100

0

400

kHz

bus free time between a STOP and

START condition

4.7

-

1.3

-

µs

hold time (repeated) START condition

4.0

-

0.6

-

µs

set-up time for a repeated START

condition

4.7

-

0.6

-

µs

set-up time for STOP condition

4.7

-

0.6

-

µs

data hold time

0

-

0

-

ns

data valid acknowledge time

-

0.6

-

0.6

µs

data valid time

SCL LOW to data out valid

-

0.6

-

0.6

ns

data set-up time

250

-

150

-

ns

LOW period of the SCL clock

4.7

-

1.3

-

µs

HIGH period of the SCL clock

4.0

-

0.6

-

µs

fall time of both SDA and SCL signals

-

300

-

300

ns

rise time of both SDA and SCL signals

-

1000

-

300

ns

pulse width of spikes that must be

suppressed by the input filter

-

50

-

50

ns

0.5

-

0.5

-

µs

I2C input pin interrupt valid time

0.2

-

0.2

-

µs

I2C input pin interrupt clear time

0.2

-

0.2

-

µs