CY7C1069AV33
Document #: 38-05255 Rev. *F
Page 9 of 9
Document History Page
Document Title: CY7C1069AV33 2M x 8 Static RAM
Document Number: 38-05255
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
113724
03/27/02
NSL
New Data Sheet
*A
117060
07/31/02
DFP
Removed 15-ns bin
*B
117990
08/30/02
DFP
Added 8-ns bin
Changing ICC for 8, 10, 12 bins
tpower changed from 1 µs to 1 ms
Load Cap Comment changed (for Tx line load)
tSD changed to 5.5 ns for the 10-ns bin
Changed some 8-ns bin #'s (tHZ, tDOE, tDBE)
Removed hz < lz comments
*C
120385
11/13/02
DFP
Final Data Sheet
Added note 4 to “AC Test Loads and Waveforms” and note 7 to tpu and tpd
Updated Input/Output Caps (for 48BGA only) to 8 pf/10 pf and for the 54-pin
TSOP to 6/8 pf
*D
124441
2/25/03
MEG
Changed ISB1 from 100 mA to 70 mA
Shaded the 48fBGA product offering information
*E
403984
See ECN
NXR
Changed the Logic Block Diagram On page # 1
Added notes under Pin Configuration
Changed the Package diagram of 51-85162 from Rev *A to Rev *D
Changed 48-Ball FBGA to 60-Ball FBGA in Pin Configuration
Updated the Ordering Information
*F
492137
See ECN
NXR
Removed 8 ns speed bin from product offering
Changed the description of IIX from Input Load Current to Input Leakage
Current in DC Electrical Characteristics table
Updated the Ordering Information
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