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STAC9758 датащи(PDF) 21 Page - Integrated Device Technology

номер детали STAC9758
подробное описание детали  HIGH-PERFORMANCE 6-CHANNEL AC??7 2.3 CODEC WITH UNIVERSAL JACKS
PDF  119 Pages
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производитель  IDT [Integrated Device Technology]
домашняя страница  http://www.idt.com
Logo IDT - Integrated Device Technology

STAC9758 датащи(HTML) 21 Page - Integrated Device Technology

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STAC9758/9759
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
PC AUDIO
IDT™
21
STAC9758/9759
V 1.2 1206
HIGH-PERFORMANCE 6-CHANNEL AC’97 2.3 CODEC WITH UNIVERSAL JACKS™
2.2.7.
AC-Link Low Power Mode Timing
2.2.8.
ATE Test Mode
Note: All AC-Link signals are normally low through the trailing edge of RESET#. Bringing
SDATA_OUT high for the trailing edge of RESET# causes the STAC9758/9759 AC-Link outputs to
go high impedance, which is suitable for ATE in-circuit testing.
Once the test mode has been entered, the STAC9758/9759 must be issued another RESET# with
all AC-Link signals low to return to the normal operating mode.
Note: # denotes an active low signal.
Parameter
Symbol
Min
Typ
Max
Units
End of Slot 2 to BIT_CLK, SDATA_IN low
Ts2_pdown
-
-
1.0
µs
Parameter
Symbol
Min
Typ
Max
Units
Setup to trailing edge of RESET# (also applies to SYNC)
Tsetup2rst
15.0
-
-
ns
Rising edge of RESET# to Hi-Z delay
Toff
-
-
25.0
ns
BIT_CLK
SDATA_IN
Note: BIT_CLK not to scale
Ts2_pdown
Don't care
Data PR4
Write to
0x20
Slot 2
Slot 1
SDATA_OUT
SYNC
Figure 6. AC-Link Low Power Mode Timing
Tsetup2rst
Hi-Z
Toff
RESET#
SDATA_OUT
SDATA_IN, BIT_CLK
Figure 7. ATE Test Mode Timing



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