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STAC9767 датащи(PDF) 16 Page - Integrated Device Technology

номер детали STAC9767
подробное описание детали  TWO-CHANNEL, 20-BIT, AC??7 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
PDF  97 Pages
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производитель  IDT [Integrated Device Technology]
домашняя страница  http://www.idt.com
Logo IDT - Integrated Device Technology

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STAC9766/9767
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
PC AUDIO
IDT™
16
STAC9766/9767
V 7.4 12/06
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
2.2.7.
AC-Link Low Power Mode Timing
Figure 7. AC-Link Low Power Mode Timing
2.2.8.
ATE Test Mode
Figure 8. ATE Test Mode Timing
Note: 1) All AC-Link signals are normally low through the trailing edge of RESET#. Bringing
SDATA_OUT high for the trailing edge of RESET# causes the STAC9766/9767 AC-Link outputs to
go high-impedance, which is suitable for ATE in-circuit testing.
Note: 2) Once the test mode has been entered, the STAC9766/9767 must be issued another
RESET# with all AC-Link signals low to return to the normal operating mode.
Note: 3) # denotes active low.
Parameter
Symbol
Min
Typ
Max
Units
BIT_CLK rise time
Triseclk
-
-
6
ns
BIT_CLK fall time
Tfallclk
-
-
6
ns
SDATA_IN rise time
Trisedin
-
-
6
ns
SDATA_IN fall time
Tfalldin
-
-
6
ns
Parameter
Symbol
Min
Typ
Max
Units
End of Slot 2 to BIT_CLK, SDATA_IN low
Ts2_pdown
-
-
1.0
µs
Parameter
Symbol
Min
Typ
Max
Units
Setup to trailing edge of RESET# (also applies to SYNC)
Tsetup2rst
15.0
-
-
ns
Rising edge of RESET# to Hi-Z delay
Toff
-
-
25.0
ns
BIT_CLK
SDATA_IN
Note: BIT_CLK not to scale
Ts2_pdown
Don't care
Data PR4
Write to
0x20
Slot 2
Slot 1
SDATA_OUT
SYNC
Tsetup2rst
Hi-Z
Toff
RESET#
SDATA_OUT
SDATA_IN, BIT_CLK



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