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ICS952906A датащи(PDF) 16 Page - Integrated Circuit Systems

номер детали ICS952906A
подробное описание детали  Programmable Timing Control Hub for Next Gen P4??processor
PDF  23 Pages
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производитель  ICST [Integrated Circuit Systems]
домашняя страница  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS952906A датащи(HTML) 16 Page - Integrated Circuit Systems

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Integrated
Circuit
Systems, Inc.
ICS952906A
1236A—08/06/07
Absolute Maximum Ratings
Stresses above those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Core Operating Voltage . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Operating Voltage . . . . . . . . . . . . . . . . . . . . . 3.6V
Lo gic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD + 0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Input High Voltage
VIH
3.3V +/-5%
2
VDD + 0.3
V
Input MID Voltage
VMID
3.3V +/-5%
1
1.8
V
Input Low Voltage
VIL
3.3V +/-5%
VSS -0.3
0.8
V
Input High Current
IIH
VIN = VDD
-5
5
uA
IIL1
VIN = 0 V; Inputs with no pull-
up resistors
-5
uA
IIL2
VIN = 0 V; Inputs with pull-up
resistors
-200
uA
Operating Supply Current
IDD3.3OP
Full Active, CL = Full load;
350
mA
all diff pairs driven
35
mA
all differential pairs tri-stated
12
mA
Input Frequency
3
Fi
VDD = 3.3 V
14.31818
MHz
3
Pin Inductance
1
Lpin
7nH
1
CIN
Logic Inputs
5
pF
1
COUT
Output pin capacitance
6
pF
1
CINX
X1 & X2 pins
5
pF
1
Clk Stabilization
1,2
TSTAB
From VDD Power-Up or de-
assertion of PD# to 1st clock.
1.8
ms
1,2
Modulation Frequency
Triangular Modulation
30
33
kHz
1
1Guaranteed by design, not 100% tested in production.
2See timing diagrams for timing requirements.
IDD3.3PD
3 Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet
ppm frequency accuracy on PLL outputs.
Input Capacitance
1
Input Low Current
Powerdown Current



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