ICS9DB801C datasheet(4/19 Pages) IDT

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IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz)

ICS9DB801C

REV C 08/16/07

ICS9DB801C

Eight Output Differential Buffer for PCI Express (50-200MHz)

Pin Description for OE_INV = 0

PIN #

PIN NAME

PIN TYPE

DESCRIPTION

GND

POWER

Ground pin.

PD#

INPUT

Asynchronous active low input pin, with 120Kohm internal pull-

up resistor, used to power down the device. The internal clocks

are disabled and the VCO and the crystal are stopped.

SRC_STOP#

INPUT

Active low input to stop SRC outputs.

HIGH_BW#

INPUT

3.3V input for selecting PLL Band Width

0 = High, 1= Low

DIF_4#

OUTPUT

0.7V differential complement clock outputs

DIF_4

OUTPUT

0.7V differential true clock outputs

VDD

POWER

Power supply, nominal 3.3V

GND

POWER

Ground pin.

DIF_5#

OUTPUT

0.7V differential complement clock outputs

DIF_5

OUTPUT

0.7V differential true clock outputs

OE_5

INPUT

Active high input for enabling outputs.

0 = tri-state outputs, 1= enable outputs

OE_6

INPUT

Active high input for enabling outputs.

0 = tri-state outputs, 1= enable outputs

DIF_6#

OUTPUT

0.7V differential complement clock outputs

DIF_6

OUTPUT

0.7V differential true clock outputs

VDD

POWER

Power supply, nominal 3.3V

OE_INV

INPUT

This latched input selects the polarity of the OE pins.

0 = OE pins active high, 1 = OE pins active low (OE#)

DIF_7#

OUTPUT

0.7V differential complement clock outputs

DIF_7

OUTPUT

0.7V differential true clock outputs

OE_4

INPUT

Active high input for enabling outputs.

0 = tri-state outputs, 1= enable outputs

OE_7

INPUT

Active high input for enabling outputs.

0 = tri-state outputs, 1= enable outputs

LOCK

OUTPUT

3.3V output indicating PLL Lock Status. This pin goes high

when lock is achieved.

IREF

INPUT

This pin establishes the reference current for the differential

current-mode output pairs. This pin requires a fixed precision

resistor tied to ground in order to establish the appropriate

current. 475 ohms is the standard value.

GNDA

POWER

Ground pin for the PLL core.

VDDA

POWER

3.3V power for the PLL core.

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