CS42526 datasheet(79/93 Pages) CIRRUS

79 / 93 page

DS585F1

CS42526

The external PLL component values listed in Table 21 have a high corner-frequency jitter-attenuation

curve, take a short time to lock, and offer good output jitter performance. It should be noted that the PLL

component values shown must be used with their associated locking modes as shown in Table 21. Use

of any other combinations of component values and locking modes may result in unstable PLL behavior.

Configuration 1 may be used for hardware and software backward-compatibility for designs originally

made with the CS42526 Revision C.

Configuration 2 may be used for hardware-only backward-compatibility for designs originally made with

the CS42526 Revision C. Using the Revision D default locking mode of ‘01’ will provide improved wide-

band jitter rejection in Double- and Quad-Speed modes.

Configuration 3 may be used for new designs with the CS42526 Revision D, or for existing designs in

which the hardware and software may be changed to use the specified PLL component values and

LOCKM[1:0] register setting. This configuration provides the best DAC and ADC performance when

clocked from the PLL recovered clock.

The Typical Connection Diagram, Figure 5 shows the recommended configuration of the two capacitors

and one resistor that comprise the PLL filter. It is important to treat the LPFILT pin as a low-level analog

input. It is suggested that the ground end of the PLL filter be returned directly to the AGND pin indepen-

dently of the digital ground plane.

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