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CS42432 датащи(PDF) 32 Page - Cirrus Logic |
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CS42432 датащи(HTML) 32 Page - Cirrus Logic |
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32 / 59 page ![]() 32 DS673F1 CS42432 FS is sampled as valid on the rising SCLK edge preceding the most significant bit of the first data sample and must be held valid for at least 1 SCLK period. Note: The ADC does not meet the timing requirements for proper operation in Quad-Speed Mode. 5.5.2 I/O Channel Allocation 5.6 AUX Port Digital Interface Formats These serial data lines are used when supporting the TDM Mode of operation with an external ADC or S/PDIF receiver attached. The AUX serial port operates only as a clock master. The AUX_SCLK will operate at 64xFs, where Fs is equal to the ADC sample rate (FS on the TDM interface). If the AUX_SDIN signal is not being used, it should be tied to AGND via a pull-down resistor. 5.6.1 Hardware Mode The AUX port will only operate in the Left-Justified digital interface format and supports bit depths ranging from 16 to 24 bits (see Figure 17 on page 34 for timing relationship between AUX_LRCK and AUX_SCLK). 5.6.2 Software Mode The AUX port will operate in either the Left-Justified or I²S digital interface format with bit depths ranging from 16 to 24 bits. Settings for the AUX port are made through the register “Miscellaneous Control (Ad- dress 04h)” on page 41. 5.6.3 I²S Digital Input/Output Interface Format Analog Output/Input Channel Allocation from/to Digital I/O DAC_SDIN TDM AOUT 1,2,3,4,5,6 ADC_SDOUT TDM AIN 1,2,3,4 (2 additional channels from AUX_SDIN) Table 4. Serial Audio Interface Channel Allocations SCLK FS 256 clks Bit or Word Wide AOUT6 LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB DAC_SDIN AOUT1 AOUT4 AOUT2 AOUT5 AOUT3 32 clks 32 clks 32 clks 32 clks 32 clks 32 clks - LSB MSB LSB MSB - 32 clks 32 clks MSB LSB - LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB ADC_SDOUT AIN1 AIN4 AIN2 - AIN3 32 clks 32 clks 32 clks 32 clks 32 clks 32 clks AUX2 LSB MSB LSB MSB AUX1 32 clks 32 clks MSB Figure 13. TDM Serial Audio Format AUX_LRCK AUX_SCLK MS B LS B MS B LS B AUX1 L e ft C h an ne l R ig h t C h an ne l AUX_SDIN AUX2 MSB Figure 14. AUX I²S Format |
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