CS42436-DMZ datasheet(61/62 Pages) CIRRUS

61 / 62 page

DS647F1

CS42436

14.ORDERING INFORMATION

15.REVISION HISTORY

Product

Description

Package

Pb-Free

Grade

Temp Range

Container

Order #

CS42436

6-in, 6-out, TDM CODEC

for Surround Sound Apps

52L-MQFP

YES

Commercial

-10° to +70° C

Rail

CS42436-CMZ

Tape & Reel CS42436-CMZR

Automotive -40° to +105° C

Rail

CS42436-DMZ

Tape & Reel CS42436-DMZR

CDB42438 CS42436 Evaluation Board

CDB42438

Revision

Changes

Initial Release

Corrected I²C Address in Section 5.7.2 on page 36.

Corrected Chip I.D. in Section 7.2.1 on page 41.

PP1

Initial Preliminary Product (PP) Release subject to legal notice below.

Added pin numbers to

“Typical Connection Diagram (Software Mode)” on page 11 and “Typical Con-

nection Diagram (Hardware Mode)” on page 12.

Changed ADC Double-Speed Mode parameters. See Note 2 on page 13 and Note 18 on page 21.

Added ADC3 MUX Interchannel Isolation characteristic in “Characteristics and Specifications” beginning on

page 13.

Changed ADC Passband Ripple maximum specifications for SSM, DSM & QSM in section “Characteristics

and Specifications” beginning on page 13.

Changed DAC Frequency Response specifications for SSM, DSM & QSM in “Characteristics and Specifica-

tions” beginning on page 13.

Removed ADC Quad-Speed Mode feature. See Note 19 on page 21.

Added section “De-Emphasis Filter” on page 32.

Corrected section “TDM data is received most significant bit (MSB) first, on the second rising edge of the

SCLK occurring after a an FS rising edge. All data is valid on the rising edge of SCLK. The AIN1 MSB is

transmitted early, but is guaranteed valid for a specified time after SCLK rises. All other bits are transmitted

on the falling edge of SCLK. Each time slot is 32 bits wide, with the valid data sample left ‘justified within the

time slot. Valid data lengths are 16, 18, 20, or 24.” on page 33.

Changed AIN1-6 Volume Control range from (+12 dB to -115.5 dB) to (+24 dB to -64 dB) in register “AINX

Volume Control (AINX_VOL[7:0])” on page 48.

Removed the register “Status Control (address 18h)”. See “CLOCK ERROR (CLK ERROR)” on

page 49

and “ADC Overflow (ADCX_OVFL)” on page 49 for the Active Mode setting.

PP2

Corrected Figures 21-23.

Added “Ordering Information” on page 61.

Updated temperature and voltage specifications in the “Recommended Operating Conditions” on page 13.

Added test conditions to the Analog Input and Analog Output Characteristics tables.

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